Current-controlled CMOS logic family

• US 20090128380A1
• Filed: 01/30/2009
• Published: 05/21/2009
• Est. Priority Date: 06/28/1999
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hairapetian, Armond
• Granted Patent: US 7,724,057 B2
• Time in Patent Office: Days
• US Class Current: 341/100
• CPC Class Codes: H03K 17/04 Modifications for accelerating switching
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/04163 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/3562 of the master-slave type

Abstract

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Claims

1. A multi-channel serial link circuit, comprising:

a first deserializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic, that is operable to convert a first differential input signal into a first deserialized signal that includes a first plurality of signals; and

a second deserializer circuit block, implemented in a parallel configuration with respect to the first deserializer circuit block and implemented using C³MOS logic, that is operable to convert a second differential input signal into a second deserialized signal that includes a second plurality of signals.

2. The multi-channel serial link circuit of claim 1, wherein:

within each of the first deserializer circuit block and the second deserializer circuit block, logic levels are signaled by current steering in one of two or more branches in response to a differential input signal.

3. The multi-channel serial link circuit of claim 1, wherein:

the first differential input signal that has a first frequency; and

each of the first plurality of signals has a second frequency.

4. The multi-channel serial link circuit of claim 3, wherein:

the second frequency is less than the first frequency.

5. The multi-channel serial link circuit of claim 3, wherein:

the first frequency is an integer multiple of the second frequency.

6. The multi-channel serial link circuit of claim 1, wherein:

the first differential input signal has a first frequency;

the second differential input signal has the first frequency;

each of the first plurality of signals has a second frequency; and

each of the second plurality of signals has the second frequency.

7. The multi-channel serial link circuit of claim 1, further comprising:

a processing circuit block, coupled to the first deserializer circuit block and the second deserializer circuit block and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to generate a plurality of processed signals.

8. The multi-channel serial link circuit of claim 7, wherein:

the first deserializer circuit block, the second deserializer circuit block, and the processing circuit block are all implemented on a single silicon die.

9. The multi-channel serial link circuit of claim 7, wherein:

the first differential input signal has a first frequency;

the second differential input signal has the first frequency;

each of the first plurality of signals has a second frequency;

each of the second plurality of signals has the second frequency; and

each of the plurality of processed signals has the second frequency.

10. The multi-channel serial link circuit of claim 9, wherein:

the second frequency is less than the first frequency.

11. The multi-channel serial link circuit of claim 9, wherein:

the first frequency is an integer multiple of the second frequency.

12. The multi-channel serial link circuit of claim 7, further comprising:

a first serializer circuit block, coupled to the processing circuit block and implemented using C³MOS logic, that is operable to convert a first portion of the plurality of processed signals into a first serialized signal; and

a second serializer circuit block, coupled to the processing circuit block, implemented in a parallel configuration with respect to the first serializer circuit block, and implemented using C³MOS logic, that is operable to convert a second portion of the plurality of processed signals into a second serialized signal.

13. The multi-channel serial link circuit of claim 12, wherein:

the first differential input signal has a first frequency;

the second differential input signal has the first frequency;

each of the first plurality of signals has a second frequency;

each of the second plurality of signals has the second frequency;

each of the plurality of processed signals has the second frequency;

the first serialized signal has a third frequency; and

the second serialized signal has the third frequency.

14. The multi-channel serial link circuit of claim 13, wherein:

the first frequency is the third frequency.

15. The multi-channel serial link circuit of claim 13, wherein:

the second frequency is less than the first frequency.

16. The multi-channel serial link circuit of claim 13, wherein:

the first frequency is an integer multiple of the second frequency.

17. The multi-channel serial link circuit of claim 1, wherein:

the multi-channel serial link circuit is implemented within a fiber optic channel.

18. The multi-channel serial link circuit of claim 1, wherein:

the first deserializer circuit block and the second deserializer circuit block are both implemented on a single silicon die.

19. A multi-channel serial link circuit, comprising:

a first serializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic, that is operable to convert a first portion of a plurality of signals into a first serialized signal; and

a second serializer circuit block, implemented in a parallel configuration with respect to the first serializer circuit block and implemented using C³MOS logic, that is operable to convert a second portion of the plurality of signals into a second serialized signal.

20. The multi-channel serial link circuit of claim 19, wherein:

within each of the first serializer circuit block and the second serializer circuit block, logic levels are signaled by current steering in one of two or more branches in response to a differential input signal.

21. The multi-channel serial link circuit of claim 19, wherein:

each of the plurality of signals has a first frequency; and

the first serialized signal has a second frequency.

22. The multi-channel serial link circuit of claim 21, wherein:

the second frequency is greater than the first frequency.

23. The multi-channel serial link circuit of claim 21, wherein:

the second frequency is an integer multiple of the first frequency.

24. The multi-channel serial link circuit of claim 19, further comprising:

a processing circuit block, coupled to each of the first serializer circuit block and the second serializer circuit block and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to generate the plurality of signals.

25. The multi-channel serial link circuit of claim 24, wherein:

the first serializer circuit block, the second serializer circuit block, and the processing circuit block are all implemented on a single silicon die.

26. The multi-channel serial link circuit of claim 24, wherein:

each of the plurality of signals has a first frequency;

the first serialized signal has a second frequency;

the second serialized signal has the second frequency.

27. The multi-channel serial link circuit of claim 26, wherein:

the second frequency is greater than the first frequency.

28. The multi-channel serial link circuit of claim 26, wherein:

the second frequency is an integer multiple of the first frequency.

29. The multi-channel serial link circuit of claim 19, wherein:

the multi-channel serial link circuit is implemented within a fiber optic channel.

30. The multi-channel serial link circuit of claim 19, wherein:

the first serializer circuit block and the second serializer circuit block are both implemented on a single silicon die.

31. A multi-channel serial link circuit, comprising:

a first deserializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic, that is operable to convert a first differential input signal into a first deserialized signal that includes a first plurality of signals; and

a second deserializer circuit block, implemented in a parallel configuration with respect to the first deserializer circuit block and implemented using C³MOS logic, that is operable to convert a second differential input signal into a second deserialized signal that includes a second plurality of signals; and

a processing circuit block, coupled to each of the first deserializer circuit block and the second deserializer circuit block and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to generate a plurality of processed signals;

a first serializer circuit block, coupled to the processing circuit block and implemented using C³MOS logic, that is operable to convert a first portion of the plurality of processed signals into a first serialized signal; and

a second serializer circuit block, coupled to the processing circuit block, implemented in a parallel configuration with respect to the first serializer circuit block, and implemented using C³MOS logic, that is operable to convert a second portion of the plurality of processed signals into a second serialized signal; and

wherein;

the first differential input signal has a first frequency;

the second differential input signal has the first frequency;

each of the first plurality of signals has a second frequency;

each of the second plurality of signals has the second frequency;

each of the plurality of processed signals has the second frequency; and

the first serialized signal has a third frequency; and

the second serialized signal has the third frequency.

32. The multi-channel serial link circuit of claim 31, wherein:

the first frequency is the third frequency.

33. The multi-channel serial link circuit of claim 31, wherein:

the second frequency is less than the first frequency.

34. The multi-channel serial link circuit of claim 31, wherein:

the first frequency is an integer multiple of the second frequency.

35. The multi-channel serial link circuit of claim 31, wherein:

the multi-channel serial link circuit is implemented within a fiber optic channel.

36. The multi-channel serial link circuit of claim 31, wherein:

the first deserializer circuit block, the second deserializer circuit block, the processing circuit block, the first serializer circuit block, and the second serializer circuit block are all implemented on a single silicon die.