SYSTEMS AND METHODS FOR PIPELINED ANALOG TO DIGITAL CONVERSION

• US 20090128391A1
• Filed: 02/05/2008
• Published: 05/21/2009
• Est. Priority Date: 11/20/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Bailey, James A., Chen, Mingdeng
• Granted Patent: US 7,551,115 B2
• Time in Patent Office: Days
• US Class Current: 341/172
• CPC Class Codes: H03M 1/168 and delivering the same number of bits

Abstract

Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide methods for performing analog to digital conversions that include providing an analog to digital converter with a residue amplifier that is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors. The methods further include performing a first sample of an analog input voltage by charging the first set of input capacitors from the analog voltage input during a first period; amplifying the first sample during a second period; performing a second sample of the analog input voltage by charging the second set of input capacitors from the analog voltage input during a third period; and amplifying the second sample during a fourth period.

Claims

1. An analog to digital converter, wherein the analog to digital converter comprises:

a residue amplifier, wherein the residue amplifier is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors, wherein the first capacitance set is separately switched from the second capacitance set, and wherein a portion of a clock cycle is provided for charging the first set of input capacitors, and a full clock cycle is provided for settling the residue amplifier.

2. The analog to digital converter of claim 1, wherein charging of the first set of input capacitors is interleaved with charging of the second set of input capacitors.

3. The analog to digital converter of claim 2, wherein charge transfer from the first set of input capacitors to the first feedback capacitor is interleaved with charge transfer from the second set of input capacitors to the second feedback capacitor.

6. The analog to digital converter of claim 1, wherein the first set of input capacitors are electrically coupled to an analog voltage input during a first period, wherein the second set of input capacitors are electrically coupled to the residue amplifier during the first period, wherein the second set of input capacitors are electrically coupled to the analog voltage input during a second period, and wherein the second set of input capacitors are electrically coupled to the residue amplifier during the second period.

7. The analog to digital converter of claim 6, wherein the analog to digital converter further includes:

a sub-adc, wherein the sub-adc receives the analog voltage input and provides a digital representation of the analog voltage input, and wherein the digital representation of the analog voltage input is used to perform a voltage subtraction from the first set of input capacitors to leave a residue value.

8. The analog to digital converter of claim 7, wherein the residue value is a first residue value, and wherein the analog to digital converter further includes:

wherein a subsequent digital representation of the analog voltage input is used to perform a voltage subtraction from the second set of input capacitors to leave a second residue value.

24. The analog to digital convener of claim 7, wherein the residue value is a first residue value, and wherein the analog to digital converter further includes:

wherein a subsequent digital representation of the analog voltage input is used to perform a voltage subtraction from the second set of input capacitors to leave a second residue value.

4-5. -5. (canceled)

9. A method for performing an analog to digital conversion, the method comprising:

providing an analog to digital converter, wherein the analog to digital converter includes a residue amplifier associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors;

performing a first sample of an analog input voltage by charging the first set of input capacitors from the analog voltage input during a first period;

amplifying the first sample during a second period;

performing a second sample of the analog input voltage by charging the second set of input capacitors from the analog voltage input during a third period;

amplifying the second sample during a fourth period; and

wherein the first period overlaps the fourth period, and wherein the third period overlaps the second period.

10. The method of claim 9, wherein the first period and the third period are each approximately one half clock cycle, and wherein the second period and the fourth period are each one full clock cycle.

11. The method of claim 9, wherein the first period and the third period are mutually exclusive.

12. The method of claim 9, wherein the second period and the fourth period are mutually exclusive.

13. The method of claim 9, wherein the method further comprises:

transferring charge from the first set of input capacitors to the first feedback capacitor during a fifth period continuing subsequent to the first period.

14. The method of claim 13, wherein the method further comprises:

transferring charge from the second set of input capacitors to the second feedback capacitor during a sixth period continuing subsequent to the third period.

15. The method of claim 9, wherein the analog to digital converter further includes:

a sub-adc, wherein the sub-adc receives the analog voltage input and provides a digital representation of the analog voltage input, wherein the digital representation of the analog voltage input is used to perform a voltage subtraction from the first set of input capacitors to leave a first residue value, and wherein a subsequent digital representation of the analog voltage input is used to perform a voltage subtraction from the second set of input capacitors to leave a second residue value.

16. The method of claim 15, wherein amplifying the first sample during a second period is amplifying the first residue value;

and wherein amplifying the second sample during a fourth period is amplifying the second residue value.

17. An analog to digital converter, wherein the analog to digital converter includes:

a residue amplifier, wherein the residue amplifier is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors, and wherein the first capacitance set is separately switched from the second capacitance set; and

a sub-adc, wherein an output from the sub-adc controls a first value subtraction from a first value maintained on the first set of input capacitors to create a first residue value, and a second value subtraction from a second value maintained on the second set of input capacitors to create a second residue value.

18. The analog to digital converter of claim 17, wherein the residue amplifier is shared between two pipeline stages.

19. The analog to digital converter of claim 17, wherein approximately one half of a clock cycle is provided for charging the first set of input capacitors to a value corresponding to an analog voltage input, and wherein a full clock cycle is provided for amplifying the first residue value.

20. The analog to digital converter of claim 19, wherein the value corresponding to the analog voltage input is a first value, wherein the approximately one half clock cycle is a first period, wherein the full clock cycle is a second period, wherein a third period corresponding in length to the first period is provided for charging the second set of input capacitors to a second value corresponding to the analog voltage input, wherein a fourth period corresponding in length to the second period is provided for amplifying the second residue value, and wherein the first period and the third period are mutually exclusive, and wherein the second period and the fourth period are mutually exclusive.

21. A pipelined analog to digital converter, wherein the pipelined analog to digital converter comprises:

a residue amplifier, wherein the residue amplifier is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors, wherein the first capacitance set is separately switched from the second capacitance set, and wherein the residue amplifier is shared between two pipeline stages.

22. An analog to digital converter, wherein the analog to digital converter comprises:

a residue amplifier, wherein the residue amplifier is associated with a first capacitance set that includes a first feedback capacitor and a first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and a second set of input capacitors, wherein the first capacitance set is separately switched from the second capacitance set, wherein the first set of input capacitors are electrically coupled to an analog voltage input during a first period, wherein the second set of input capacitors are electrically coupled to the residue amplifier during the first period, wherein the second set of input capacitors are electrically coupled to the analog voltage input during a second period, and wherein the second set of input capacitors are electrically coupled to the residue amplifier during the second period.

23. The analog to digital convener of claim 22, wherein the analog to digital converter further includes:

a sub-adc, wherein the sub-adc receives the analog voltage input and provides a digital representation of the analog voltage input, and wherein the digital representation of the analog voltage input is used to perform a voltage subtraction from the first set of input capacitors to leave a residue value.