Spatial light modulator implemented with a mirror array device

• US 20090128465A1
• Filed: 11/13/2008
• Published: 05/21/2009
• Est. Priority Date: 11/16/2007
• Status: Abandoned Application

• Current Assignee: Olympus Corporation, Silicon Quest Kabushiki-Kaisha
• Original Assignee: Olympus Corporation, Silicon Quest Kabushiki-Kaisha
• Inventors: Maeda, Yoshihiro, Sugimoto, Naoya, Arai, Kazuma, Shirai, Akira, Ishii, Fusao
• Application Number:
  US12/291,941
• Publication Number:
  US 20090128465A1
• Time in Patent Office: Days
• US Class Current: 345/84
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 3/2081 with combination of amplitude modulation and time modulation space and time error diffusion G09G3/2066
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833

Abstract

The present invention provides a spatial light modulator, comprising: a plurality of pixel units configured as a two dimensional array extending in a vertical direction and a horizontal direction; a plurality of row lines each comprises a word line and a plate line connected to a plurality of the pixel units along a row in the horizontal direction; a first address decoder for selecting the word line; a second address decoder for selecting the plate line; and a level retention circuit interconnected between the plate line and second address decoder to retain a voltage level of the plate line.

Claims

1. A spatial light modulator, comprising:

a plurality of pixel units arranged as a pixel array along a vertical and a horizontal directions;

a plurality of row lines each comprises a word line and a plate line and each connected to a plurality of the pixel units;

a first address decoder connected to said word lines for selecting and activating selected word lines;

a second address decoder connected to said plate lines for selecting and activating selected plate lines; and

a level retention circuit interconnected between the plate line and the second address decoder to retain the voltage level of the plate line.

2. The spatial light modulator according to claim 1, wherein:

said plate lines are divide into a plurality of groups and the second address decoder controls said plate lines in each of said group independently.

3. A spatial light modulator, comprising:

a plurality of pixel units arranged as a two-dimensional pixel array extending along a vertical and a horizontal directions;

a plurality of row lines each includes a word line and a plate line and each connected to a plurality of the pixel units;

a first address decoder connected to the word lines for selecting and activating selected word lines; and

a second address decoder and a third address decoder share and select the plate lines.

4. The spatial light modulator according to claim 3, further comprising:

level retention circuits interconnected between the plate lines and the second address decoder, and between the plate lines and the third address decoder to retain voltage levels of the plate lines.

5. The spatial light modulator according to claim 3, wherein:

each of the row lines is alternately addressed by the second and third address decoders.

6. The spatial light modulator according to claim 3, wherein:

the second and third address decoders alternately address different row lines.

7. A spatial light modulator, comprising:

a plurality of pixel units configured as a two-dimensional pixel array extended along a vertical direction and a horizontal direction;

a plurality of row lines each comprises a word line and a plate line connected to a plurality of the pixel units disposed along a row in said two-dimensional pixel array;

a first address decoder connected to the word lines for selecting and activating the selected word line; and

a second address decoder connected to said plate lines for selecting and activating the selected plate line.

8. The spatial light modulator according to claim 7, wherein:

the second address decoder selects the plate line continuously for at least twice in a display frame period.

9. A mirror array device, comprising:

a video image controller for transmitting a digital image data according to a video image signal;

a plurality of mirror elements arranged as a pixel array for modulating an illumination light in accordance with the digital image data corresponding to the video image signal;

each of the mirror elements further comprises a memory circuit;

a bit line for transmitting a first data signal to the memory circuit;

a word line for selecting a plurality of memory circuits disposed on a selected row;

a plate line for transmitting a second data signal to the memory circuits disposed on a selected row;

a first address decoder for selecting the word line in accordance with the digital image data; and

a second address decoder for selecting the plate line when a predetermined delay time elapses after the word line is selected.

10. The mirror array device according to claim 9, wherein:

the first address decoder selects all of the word lines at least once in one frame period, while the second address decoder selects all of the plate lines at least twice in the one frame period.

11. The mirror array device according to claim 9, wherein:

the second address decoder selects and independently controls the plate lines in at least two separate regions, wherein

the plate lines in the at least two separate regions are selected at least once in the one frame period.

12. The mirror array device according to claim 9, wherein:

the predetermined delay time is maintained as a constant delay within one frame period.

13. The mirror array device according to claim 9, wherein:

the predetermined delay time is determined by a quantity of the illumination light projected from a light source or a quantity of a reflection light from the mirror element.

14. The mirror array device according to claim 9, wherein:

each of the mirror elements has an ON state, an OFF state and an oscillation state, wherein

each of the plate lines is selected for shifting one of the mirror elements from the ON or OFF state to the oscillation state.

15. The mirror array device according to claim 9, wherein:

said pixel array comprises approximately 900 thousand mirror elements or more, wherein

each mirror has a mirror surface area ranging between 25 square micrometers and 100 square micrometers.

16. The mirror array device according to claim 9, wherein:

the pixel array has at least 720 row lines extending along a horizontal direction.

17. The mirror array device according to claim 9, wherein:

the mirror elements are arranged as a two-dimensional array extending along a vertical direction and a horizontal direction wherein;

the first data signal from the bit line is transmitted to the memory circuits connected to one line in the horizontal direction at a rate of 23 nanoseconds or less.

18. The mirror array device according to claim 9, wherein:

the plate lines have a data transmission speed for transmitting the second data signal to the memory circuit higher than a data transmission speed of the first data signal on the bit lines for writing data to the memory circuits.

19. A spatial light modulator, comprising:

a plurality of pixel units arranged as a two-dimensional pixel array extending in a vertical and a horizontal directions;

a plurality of row lines, each of row lines comprise a plurality of the pixel units along the horizontal direction wherein said row lines are divided into an upper region and a lower region in the vertical direction;

each of the row lines further comprises a word line and plate line;

a first address decoder for controlling the word line;

a second address decoder for controlling the plate lines of the upper region; and

a third address decoder for controlling the plate lines of the lower region.

20. The spatial light modulator according to claim 19, wherein:

the second and third address decoders control each of the plate lines in substantially a simultaneously manner.