Spin transfer MRAM device with separated CPP assisted writing

• US 20090129143A1
• Filed: 11/21/2007
• Published: 05/21/2009
• Est. Priority Date: 11/21/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: MagIC Technologies Inc (TDK Corporation)
• Inventors: Guo, Yimin, Chien, Jeff
• Granted Patent: US 7,577,021 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10B 61/20 comprising components having three or more electrodes, e.g. transistors
• CPC Class Codes: Y10S 977/935 Spin dependent tunnel, SDT, junction, e.g. tunneling magnetoresistance, TMR

Abstract

A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in each bit cell have different resistance states and the MTJ cell and CPP cell in each sub-cell have different resistance states. The MTJ free layer rotates in response to switching in the CPP free layer because of a large demagnetization field exerted by the CPP free layer. An improved circuit design is disclosed that enables a faster and more reliable read process since the reference is a second MTJ within the same bit cell. When R_MTJ1>R_MTJ2, the bit cell has a “0” state, and when R_MTJ1<R_MTJ2, the bit cell has a “1” state.

Claims

1. A spin-transfer MRAM structure comprising a bit cell array wherein each bit cell has two sub-cells which are a first sub-cell and a second sub-cell, and each sub-cell comprises:

(a) a MTJ cell formed on a bottom electrode wherein the MTJ cell has a first free layer and a first synthetic pinned layer that are separated by a tunnel barrier layer, said MTJ cell has a near zero anisotropy, and said first free layer has a magnetization that is oriented anti-parallel to a magnetization direction in an overlying second free layer in a CPP cell such that when the second free layer is switched by a write current, the first free layer is also switched through a magnetic coupling interaction with the second free layer;

(b) a conductive spacer layer formed on the MTJ cell; and

(c) a CPP cell with a top electrode and formed on the conductive spacer wherein the CPP cell is comprised of a second free layer and a second synthetic pinned layer separated by a non-magnetic spacer, and said CPP cell has a substantial anisotropy, and said second free layer has a magnetization that is switched either by a write current flowing from a bit line contacting the top electrode through the CPP cell and then to the conductive spacer, or from the conductive spacer through the CPP cell and then to the bit line contacting the top electrode;

and wherein the MTJ cell and CPP cell in each sub-cell have a different resistance state, the two MTJ cells in each bit cell have different resistance states, and the two CPP cells in each bit cell have different resistance states.

2. The spin-transfer MRAM structure of claim 1 wherein said MTJ cell in each sub-cell has a structure in which a seed layer, a first AFM (AFM1) layer, a first pinned layer represented by AP1/coupling layer/AP2, a tunnel barrier layer, the first free layer, and a capping layer are sequentially formed on the bottom electrode, and said first free layer is a single layer or composite of soft magnetic materials.

3. The spin-transfer MRAM structure of claim 1 wherein each of said MTJ cells has a substantially circular shape with a first free layer having a near zero anisotropy of less than about 5 Oe, and each of said CPP cells has an elliptical shape, eye shape, or another rounded shape from a top-down view with a second free layer having an anisotropy of greater than about 50 Oe.

4. The spin-transfer MRAM structure of claim 1 wherein each of said MTJ cells has a first area size from a top-down view, and each of said CPP cells has a second area size from a top-down view that is greater than the first area size.

5. The spin-transfer MRAM structure of claim 1 wherein the conductive spacer is comprised of a highly conductive material that is one of Cu, Au, Ag, or Al.

6. The spin-transfer MRAM structure of claim 1 wherein each of said CPP cells has a structure in which a seed layer, a second free layer, a non-magnetic spacer, first AFM (AFM1) layer, a second SyAF pinned layer represented by AP3/coupling layer/AP4, a second AFM (AFM2) layer, and a second capping layer are sequentially formed on the conductive spacer, and said second free layer is a single layer or composite of soft magnetic materials that has a low damping ratio, and said second seed layer is made of Cu, Au, Ag, or Al so that the low damping ratio will not be degraded.

7. The spin-transfer MRAM structure of claim 1 wherein the second free layer has an anisotropy which is sufficiently large enough to assure a thermal factor K_UM_SV/k_BT>

40 where K_U is the anisotropy constant, Ms is the saturation magnetization, V is the volume of the FM2 free layer, k_B is the Boltzmann constant, and T is the temperature.

8. The spin-transfer MRAM structure of claim 1 further comprised of a circuit that enables the bit sub-cells to be written to and read, comprising:

(a) a first bit line which contacts the top electrode in the CPP cell in a first bit sub-cell and a second bit line that contacts the top electrode in the CPP cell in a second bit sub-cell;

(b) a write word line that controls a transistor formed between the conductive spacer in a first bit sub-cell and the conductive spacer in a second bit sub-cell, said write word line is aligned orthogonal to said first bit line and second bit line;

(c) a read word line that controls two read transistors wherein a first bottom electrode which contacts the MTJ cell in a first bit sub-cell is connected to a ground voltage through a first read transistor, and a second bottom electrode that contacts the MTJ cell in the second bit sub-cell is connected to a ground voltage through a second read transistor; and

(d) a sense amplifier for comparing a resistance in the MTJ cell in said first bit sub-cell with a resistance in the MTJ cell in said second bit sub-cell.

9. The spin-transfer MRAM of claim 7 wherein the bit cell has a “

0”

resistance state when the MTJ cell in said first bit sub-cell has a greater resistance than the resistance of the MTJ cell in the second bit sub-cell, and the bit cell has a “

1”

resistance state when the MTJ cell in said first bit sub-cell has a lower resistance than the resistance of the MTJ cell in the second sub-cell.

10. A method of forming a bit cell in a spin-transfer MRAM structure wherein each bit cell is comprised of two sub-cells, comprising:

(a) forming a bottom electrode in each sub-cell, each of said bottom electrodes are connected to a ground voltage through a read transistor;

(b) forming a MTJ cell on each bottom electrode, said MTJ cell is comprised of a first free layer that has near zero anisotropy, and has a capping layer as a top surface;

(c) forming a conductive spacer on said capping layer; and

(d) forming a CPP cell on said conductive spacer, said CPP cell is comprised of a second free layer that has a substantial anisotropy, and has a capping layer as a top electrode.

11. The method of claim 10 wherein the MTJ cell is fabricated by sequentially forming a first seed layer, a first AFM (AFM1) layer, a first SyAF pinned layer having a AP1/coupling/AP2 configuration, a tunnel barrier layer, a first free layer, and a first capping layer on the bottom electrode, and said CPP cell is fabricated by sequentially forming a seed layer, a second free layer, a non-magnetic spacer, a second SyAF pinned layer having a AP3/coupling/AP4 configuration, a second AFM (AFM2) layer, and a capping layer on the conductive spacer.

12. The method of claim 11 further comprised of a high temperature annealing with a large external magnetic field that sets the exchange pinning direction of the AFM1 and AFM2 layers and thereby pins the magnetization directions of the first SyAF pinned layer and second SyAF pinned layer, respectively, such that the AP1 magnetization and AP4 magnetization are aligned in the same direction.

13. The method of claim 11 further comprised of forming a first bit line that contacts the top electrode in the CPP cell in the first sub-cell and forming a second bit line that contacts the top electrode in the CPP cell in the second sub-cell.

14. The method of claim 11 wherein the CPP cell has an area size that is larger than an area size of the MTJ cell from a top-down view.

15. The method of claim 11 wherein the second free layer anisotropy is about 3 to 1000 times greater than the first free layer anisotropy.

16. The method of claim 11 further comprised of forming a transistor controlled by a write word line, said transistor is connected to a first conductive spacer in a first sub-cell and to a second conductive spacer in a second sub-cell and enables a write current to flow from one conductive spacer to a second conductive spacer within the same bit cell.

17. A method of writing a “

0”

resistance state to a bit cell in a spin-transfer MRAM structure wherein the bit cell is comprised of two sub-cells each having a CPP cell formed above a MTJ cell and connected through a conductive spacer, each of said MTJ cells has a first free layer with near zero anisotropy, and each of said CPP cells has a second free layer with a substantial anisotropy and a top electrode contacting a bit line, and a first conductive spacer in first sub-cell and a second conductive spacer in a second sub-cell are connected through a transistor, comprising;

(a) injecting a write current into a first bit line contacting a top electrode in the CPP cell in the first sub-cell, said write current passes through the first CPP cell and into the first conductive spacer and then into the second conductive spacer and out through a second CPP cell to a second bit line contacting the top electrode in the second CPP cell to form a “

0”

resistance state in the first CPP cell, a “

1”

resistance state in the first MTJ cell, a “

1”

resistance state in the second CPP cell, and a “

0”

resistance state in the second MTJ cell; and

(b) simultaneously applying a current to a write word line that controls a voltage to said transistor and causes current to flow from the first conductive spacer to the second conductive spacer.

18. A method of writing a “

1”

resistance state to a bit cell in a spin-transfer MRAM structure wherein the bit cell is comprised of two sub-cells each having a CPP cell formed above a MTJ cell and connected through a conductive spacer, each of said MTJ cells has a first free layer with near zero anisotropy, and each of said CPP cells has a second free layer with a substantial anisotropy and a top electrode contacting a bit line, and a first conductive spacer in first sub-cell and a second conductive spacer in a second sub-cell are connected through a transistor, comprising;

(a) injecting a write current into a second bit line contacting a top electrode in the CPP cell in the second sub-cell, said write current passes through the second CPP cell and into the second conductive spacer and then into the first conductive spacer and out through a first CPP cell to a first bit line contacting the top electrode in the first sub-cell to form a “

1”

resistance state in the first CPP cell, a “

0”

resistance state in the first MTJ cell, a “

0”

resistance state in the second CPP cell, and a “

1”

resistance state in the second MTJ cell; and

(b) simultaneously applying a current to a write word line that controls a voltage to said transistor and causes current to flow from the second conductive spacer to the first conductive spacer.

19. A method of reading a resistance state of a bit cell in a spin-transfer MRAM structure wherein the bit cell is comprised of two sub-cells each having a CPP cell formed above a MTJ cell and connected through a conductive spacer, each of said MTJ cells has a first free layer with near zero anisotropy and is formed on a bottom electrode that is grounded through a read transistor wherein said read transistors are controlled by a read word line, and each of said CPP cells has a second free layer with a substantial anisotropy and a top electrode connected to a bit line, and a first conductive spacer in first sub-cell and a second conductive spacer in a second sub-cell are connected through a transistor, comprising:

(a) biasing a first bit line connected to a first CPP cell and biasing a second bit line connected to a second CPP cell with a certain voltage; and

(b) applying a current to said read word line that applies a voltage to said read transistors and enables a sense amplifier to detect the resistance state in the MTJ cell in each sub-cell.

20. The method of claim 19 wherein said certain voltage used for biasing the first bit line a second bit line is from about 0.05 to 0.5 volts.

21. The method of claim 19 wherein a “

0”

resistance state for the bit cell is detected when the resistance in the MTJ in the first sub-cell is greater than the resistance of the MTJ in the second sub-cell, and a “

1”

resistance state for the bit cell is detected when the resistance in the MTJ in the second sub-cell is greater than the resistance of the MTJ in the first sub-cell.