Memory Cell Array Comprising Floating Body Memory Cells

• US 20090129145A1
• Filed: 11/19/2007
• Published: 05/21/2009
• Est. Priority Date: 11/19/2007
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Slesazeck, Stefan
• Granted Patent: US 7,719,869 B2
• Time in Patent Office: Days
• US Class Current: 365/174
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A memory cell array includes a plurality of floating body memory cells, which are arranged in cell rows, and world lines, wherein each word line is configured to control memory cells associated with a pair of cell rows. The memory cell array also includes bitlines, wherein each bitline is electrically connected to an individual memory cell of each pair of the cell rows.

Claims

1. An integrated circuit including a memory cell array comprising:

a plurality of memory cells arranged in cell rows, wherein each memory cell comprises a floating semiconductor body and is configured to store charge in the floating semiconductor body;

a plurality of word lines, wherein each word line is configured to control memory cells assigned to a pair of cell rows; and

a plurality of bit lines, wherein each bit line is electrically connected to an individual memory cell of each pair of cell rows.

2. The integrated circuit of claim 1, wherein the individual word lines are respectively arranged between two neighboring cell rows of memory cells.

3. The integrated circuit of claim 1, wherein each word line is arranged in a word line trench formed between neighboring cell rows in a main surface of a semiconductor substrate.

4. The integrated circuit of claim 1, wherein each memory cell further comprises:

a first electrode region disposed between the floating semiconductor body of the memory cell and a bulk portion of a semiconductor substrate, in which the memory cells are formed.

5. The integrated circuit of claim 4, wherein the first electrode regions are connected to each other.

6. The integrated circuit of claim 4, wherein each memory cell further comprises:

a second electrode region facing the first electrode region at an opposing side of the floating semiconductor body, wherein each second electrode region is electrically connected to one of the bit lines.

7. The integrated circuit of claim 6, wherein the first electrode region forms a first source/drain region and the second electrode region forms a second source/drain region of a floating body field effect transistor.

8. The integrated circuit of claim 7, wherein an upper edge of the word lines is formed below an upper edge of the second source/drain regions.

9. The integrated circuit of claim 4, wherein:

the first electrode regions form a cathode region; and

each memory cell further comprises;

an avalanche region facing the cathode electrode region at an opposing side of the floating semiconductor body; and

an anode region facing the floating semiconductor body at an opposing side of the avalanche region, wherein each anode electrode region is electrically connected to one of the bit lines and the anode and the cathode electrodes form terminals of a floating body thyristor.

10. The integrated circuit of claim 1, wherein:

the word lines run along a first direction; and

the bit lines run along a second direction, the first direction being perpendicular the second direction.

11. The integrated circuit of claim 10, further comprising:

a plurality of insulator structures, wherein each insulator structure is disposed between neighboring memory cells and runs along the first direction.

12. The integrated circuit of claim 10, wherein the memory cells are further arranged along cell columns running along a third direction that is tilted with respect to the first and second directions.

13. The integrated circuit of claim 12, wherein the third direction intersects the first direction at an angle from 25 to 65 degrees.

14. The integrated circuit of claim 1, further comprising:

a first word line driver circuit configured to supply a write signal to a first group of word lines; and

a second word line driver circuit configured to supply a read signal to a second group of word lines, the read signal differing from the write signal;

wherein word lines of the first and second group are arranged in alternating order.

15. The integrated circuit of claim 1, further comprising:

a multiple voltage word line driver circuit configured to supply a write signal and a read signal to a first group of word lines; and

a back gate driver circuit configured to supply a constant voltage to a second group of word lines;

wherein word lines of the first and second group are arranged in alternating order.

16. The integrated circuit of claim 15, wherein

the multiple voltage word line driver circuit comprises two portions facing each other at opposing sides of the memory cell array.

17. An integrated circuit including a memory cell array comprising:

a plurality of memory cells arranged in cell rows, wherein each memory cell comprises a floating semiconductor body and is configured to store charge in the floating semiconductor body; and

a plurality of word lines, each word line being configured to control the memory cells of a pair of cell rows and being arranged in a word line trench formed between neighboring cell rows in a main surface of a semiconductor substrate, wherein an upper edge of each word line is formed below the main surface.

18. The integrated circuit of claim 17, wherein the individual word lines are respectively arranged between each pair of neighboring cell rows.

19. An integrated circuit including:

a plurality of memory cells arranged in cell rows, wherein each memory cell comprises a floating semiconductor body and is configured to store charge in the floating semiconductor body;

a plurality of word lines, wherein each word line controls memory cells assigned to a pair of neighboring cell rows;

a first word line driver circuit configured to supply a write voltage to a first group of word lines; and

a second word line driver circuit configured to supply a read voltage to a second group of word lines, wherein word lines of the first and second groups are arranged in alternating order.

20. The integrated circuit of claim 19, further comprising:

a plurality of bit lines, wherein each bit line is electrically connected to an individual memory cell of each pair of cell rows.

21. A method of operating an integrated circuit comprising a memory cell array including floating body memory cells arranged in cell rows, the method comprising:

applying a write signal to a first word line that extends along a first side of a first one of the cell rows to write data into first memory cells associated to the first one of the cell rows; and

applying a read signal to a second word line that extends along a second side of the first one of the cell rows to read data from at least a part of the first memory cells associated to the first one of the cell rows.

22. The method of claim 21, wherein the word lines and the cell rows extend along a first direction and alternate along a second direction that is perpendicular to the first direction.

23. The method of claim 22, wherein applying the write signal further comprises:

writing data into second memory cells associated with a second one of the cell rows facing the first one of the cell rows at an opposing side of the first word line.

24. The method of claim 23, wherein applying the read signal further comprises:

applying the read signal to a third word line facing the first word line at the second one of the cell rows; and

selecting bit lines, wherein the data is read out from the memory cells of two cell rows associated with the third word line.

25. The method of claim 23, wherein applying a read signal further comprises:

selecting a first group of bit lines, wherein the bit lines of the first group are associated with the first memory cells, to read out first data from the first memory cells and latching the first data; and

applying the read signal to a third word line facing the first word line at the second one of the cell rows and selecting a second group of bit lines associated with the second memory cells to read out second data from the second memory cells and combining the first and second data.