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Memory Cell Array Comprising Floating Body Memory Cells

  • US 20090129145A1
  • Filed: 11/19/2007
  • Published: 05/21/2009
  • Est. Priority Date: 11/19/2007
  • Status: Active Grant
First Claim
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1. An integrated circuit including a memory cell array comprising:

  • a plurality of memory cells arranged in cell rows, wherein each memory cell comprises a floating semiconductor body and is configured to store charge in the floating semiconductor body;

    a plurality of word lines, wherein each word line is configured to control memory cells assigned to a pair of cell rows; and

    a plurality of bit lines, wherein each bit line is electrically connected to an individual memory cell of each pair of cell rows.

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