NONVOLATILE SEMICONDUCTOR STORAGE DEVICE

• US 20090129155A1
• Filed: 11/17/2008
• Published: 05/21/2009
• Est. Priority Date: 11/20/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: IWAMOTO, Masao, SUZUKI, Takahiro, HONDA, Yasuhiko, KINJO, Kiyochika
• Granted Patent: US 7,843,728 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell.

Claims

1. A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell,

wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and

in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell.

2. The nonvolatile semiconductor storage device according to claim 1, wherein an address space in the second unit is controlled as the pseudo binary state or the multivalued state,

in a case where the memory cell is in the pseudo binary state, first flag data is stored for each second unit, and in a case where the memory cell is in the multivalued state, second flag data is stored for each second unit,

in a case where neither the first flag data nor the second flag data is stored, data processing by both the first write operation and the second write operation is permitted,

in a case where the first flag data is stored and the second flag data is not stored, data processing by the first write operation is permitted, and data processing by the second write operation is inhibited, and

in a case where the second flag data is stored and the first flag data is not stored, both data processing by the first write operation and data processing by the second write operation are inhibited.

3. The nonvolatile semiconductor storage device according to claim 2, wherein in a case where data processing by the first write operation is performed, the first flag data and the second flag data corresponding to a designated address space are read, and if it is determined that the designated address space is in the pseudo binary state, data processing is performed by omitting writing of the first flag data.

4. The nonvolatile semiconductor storage device according to claim 2, wherein the first flag data is stored in the memory cell that stores the parity data, and

the second flag data is stored in the one memory cell as the pseudo binary state.

5. The nonvolatile semiconductor storage device according to claim 3, wherein the first flag data is stored in the memory cell that stores the parity data, and

the second flag data is stored in the one memory cell as the pseudo binary state.

6. The nonvolatile semiconductor storage device according to claim 2, wherein in a case where the first flag data is stored, data corresponding to an address space whose logic is fixed is not read, and input data corresponding to an address space whose logic is not fixed is read.

7. The nonvolatile semiconductor storage device according to claim 3, wherein in a case where the first flag data is stored, data corresponding to an address space whose logic is fixed is not read, and input data corresponding to an address space whose logic is not fixed is read.

8. The nonvolatile semiconductor storage device according to claim 4, wherein in a case where the first flag data is stored, data corresponding to an address space whose logic is fixed is not read, and input data corresponding to an address space whose logic is not fixed is read.

9. The nonvolatile semiconductor storage device according to claim 5, wherein in a case where the first flag data is stored, data corresponding to an address space whose logic is fixed is not read, and input data corresponding to an address space whose logic is not fixed is read.

10. A nonvolatile semiconductor storage device, comprising:

a plurality of memory cells capable of reading and writing of data;

a flag storing part that stores flag data indicating which of multivalued data writing and binary data writing is performed for each predetermined cell region, which constitutes a part of the plurality of memory cells; and

an access range setting part that permits access to the whole of the corresponding cell region based on an external address in a case where the flag data indicates the multivalued data writing and permits access to a half of the corresponding cell region based on successive external addresses in an address range in a case where the flag data indicates the binary data writing.

11. The nonvolatile semiconductor storage device according to claim 10, wherein the access range setting part has an address converting part that rearranges at least a part of a bit sequence constituting an external address in a case where the flag data indicates the binary data writing.

12. The nonvolatile semiconductor storage device according to claim 10, further comprising:

a parity storing part that stores parity data used for error correction in a case where the flag data indicates the multivalued data writing,

wherein the flag storing part and the parity storing part are provided in a part of the plurality of memory cells.

13. The nonvolatile semiconductor storage device according to claim 11, further comprising:

a parity storing part that stores parity data used for error correction in a case where the flag data indicates the multivalued data writing,

wherein the flag storing part and the parity storing part are provided in a part of the plurality of memory cells.

14. The nonvolatile semiconductor storage device according to claim 10, wherein the size of the cell region in binary data writing is the size of a page, which is a unit of multivalued data writing, or the size of an erase block, which is an unit of data erasure of the plurality of memory cells.

15. The nonvolatile semiconductor storage device according to claim 11, wherein the size of the cell region in binary data writing is the size of a page, which is a unit of multivalued data writing, or the size of an erase block, which is an unit of data erasure of the plurality of memory cells.

16. The nonvolatile semiconductor storage device according to claim 12, wherein the size of the cell region in binary data writing is the size of a page, which is a unit of multivalued data writing, or the size of an erase block, which is an unit of data erasure of the plurality of memory cells.

17. The nonvolatile semiconductor storage device according to claim 13, wherein the size of the cell region in binary data writing is the size of a page, which is a unit of multivalued data writing, or the size of an erase block, which is an unit of data erasure of the plurality of memory cells.

18. The nonvolatile semiconductor storage device according to claim 10, wherein the size of the cell region in binary data writing is any size ranging from the size of a page, which is a unit of multivalued data writing, to the size of the whole of the plurality of memory cells.

19. The nonvolatile semiconductor storage device according to claim 11, wherein the size of the cell region in binary data writing is any size ranging from the size of a page, which is a unit of multivalued data writing, to the size of the whole of the plurality of memory cells.

20. The nonvolatile semiconductor storage device according to claim 12, wherein the size of the cell region in binary data writing is any size ranging from the size of a page, which is a unit of multivalued data writing, to the size of the whole of the plurality of memory cells.