SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INCREASING A LIFETIME OF A PLURALITY OF BLOCKS OF MEMORY

• US 20090129163A1
• Filed: 11/19/2007
• Published: 05/21/2009
• Est. Priority Date: 11/19/2007
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: SandForce, Inc. (Broadcom, Inc.)
• Inventors: Danilak, Radoslav
• Granted Patent: US 7,903,486 B2
• Time in Patent Office: Days
• US Class Current: 365/185.90
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 : Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/349 : Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 : Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 17/00 : Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: G11C 29/04 : Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents

Abstract

A system, method, and computer program product are provided for increasing a lifetime of a plurality of blocks of memory. In operation, at least one factor that affects a lifetime of a plurality of blocks of memory is identified. Additionally, the plurality of blocks to write is selected, based on the at least one factor.

Claims

1. A method, comprising:

identifying at least one factor that affects a lifetime of a plurality of blocks of memory; and

selecting which of the plurality of blocks to write, based on the at least one factor.

2. The method of claim 1, wherein the at least one factor includes a number of errors during a read operation involving at least one of the blocks of memory.

3. The method of claim 2, wherein the errors are detected errors.

4. The method of claim 2, wherein the errors are corrected errors.

5. The method of claim 1, wherein the at least one factor includes a duration between a program operation and a read operation involving at least one of the blocks of memory.

6. The method of claim 1, wherein the at least one factor includes a number of times at least one of the blocks of memory is erased.

7. The method of claim 1, wherein the at least one factor includes a duration required to erase at least one of the blocks of memory.

8. The method of claim 1, wherein the at least one factor includes a duration required to program at least one of the blocks of memory.

9. The method of claim 1, wherein the at least one factor includes a number of retries required to program at least one of the blocks of memory.

10. The method of claim 1, wherein the at least one factor includes a number of intervening reads of a page of at least one of the blocks of memory.

11. The method of claim 1, wherein the at least one factor includes a number of intervening reads in a neighboring page.

12. The method of claim 1, and further comprising calculating a score, based on the at least one factor.

13. The method of claim 12, wherein the selecting is based on the score.

14. The method of claim 1, wherein the selecting is based on a plurality of the factors.

15. The method of claim 1, wherein a first one of the blocks with a longer estimated lifetime is written before a second one of the blocks with a shorter estimated lifetime.

16. The method of claim 15, wherein the second one of the blocks with the shorter estimated lifetime is above a threshold.

17. The method of claim 16, wherein the first one of the blocks with the longer estimated lifetime is below a threshold.

18. The method of claim 1, wherein the memory includes a mechanical storage device.

19. The method of claim 1, wherein the memory includes a volatile memory device.

20. The method of claim 1, wherein the memory includes a nonvolatile memory device.

21. The method of claim 20, wherein the nonvolatile memory device includes at least one of a single-bit per cell NOR flash memory, a multi-bit per cell NOR flash memory, a single-bit per cell NAND flash memory, and a multi-bit per cell NAND flash memory.

22. The method of claim 1, further including storing a history of use of the plurality of blocks of memory.

23. A computer program product embodied on a computer readable medium, comprising:

computer code for identifying at least one factor that affects a lifetime of a plurality of blocks of memory; and

computer code for selecting which of the plurality of blocks to write, based on the at least one factor.

24. An apparatus, comprising:

logic for selecting which of a plurality of blocks to write, based on at least one factor that affects a lifetime of the plurality of blocks of memory.

25. The apparatus of claim 24, wherein the logic is coupled between a system and the memory.