Nonvolatile Memory Devices and Methods of Operating Same to Inhibit Parasitic Charge Accumulation Therein
First Claim
1. A method of operating a nonvolatile memory device, comprising:
- erasing a first string of nonvolatile memory cells in the nonvolatile memory device by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which are interleaved with the first plurality of nonvolatile memory cells.
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Accused Products
Abstract
Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells. The operation to selectively erase the second plurality of nonvolatile memory cells may include erasing the second plurality of nonvolatile memory cells while simultaneously biasing the first plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the first plurality of nonvolatile memory cells.
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Citations
29 Claims
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1. A method of operating a nonvolatile memory device, comprising:
erasing a first string of nonvolatile memory cells in the nonvolatile memory device by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which are interleaved with the first plurality of nonvolatile memory cells. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A nonvolatile memory device, comprising:
an array of nonvolatile memory cells electrically coupled to a plurality of functional word lines that extend over corresponding channel regions of the nonvolatile memory cells in said array and a plurality of dummy word lines that respectively extend between corresponding pairs of functional word lines. - View Dependent Claims (8, 9)
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10. A method of operating a string of nonvolatile memory cells, comprising:
erasing at least a first nonvolatile memory cell within the string by biasing a first word line associated with the first nonvolatile memory cell at a first voltage having a magnitude sufficient to establish or exceed a critical erase voltage between the first word line and a channel region of the first nonvolatile memory cell while concurrently biasing a second word line associated with a second nonvolatile memory cell extending immediately adjacent the first nonvolatile memory cell at a second voltage having a magnitude insufficient to establish a critical erase voltage between the second word lines and a channel region of the second nonvolatile memory cell. - View Dependent Claims (11)
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12. A nonvolatile memory device, comprising:
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a nonvolatile memory cell comprising a word line on a semiconductor substrate and first and second source/drain regions within a semiconductor substrate; and first and second dummy word lines on the first and second source/drain regions, respectively. - View Dependent Claims (13)
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14. A memory device, comprising:
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a nonvolatile memory array having a plurality of rows of charge trap memory cells therein that are electrically coupled to a respective plurality of word lines; and a voltage generator electrically coupled to the plurality of word lines, said voltage generator configured to drive a first plurality of the word lines with an erase voltage and concurrently drive a second plurality of the word lines with a blocking voltage, unequal to the erase voltage, during an operation to erase the nonvolatile memory array. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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22. A method of operating a nonvolatile memory device, comprising:
erasing a first memory cell in a string of nonvolatile memory cells by establishing a first voltage difference between a gate of the first memory cell and a well region of the first memory cell while concurrently establishing a second voltage difference, which is less than the first voltage difference, between a gate of a second memory cell in the string and a well region of the second memory cell. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
Specification