MULTI-PORT THIN-FILM MEMORY DEVICES

• US 20090129174A1
• Filed: 07/14/2008
• Published: 05/21/2009
• Est. Priority Date: 11/19/2007
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Raminda Madurawe
• Inventors: Madurawe, Raminda
• Granted Patent: US 7,635,988 B2
• Time in Patent Office: Days
• US Class Current: 365/189.80
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

In a first aspect, a semiconductor storage device, comprising: a metal line coupled to a gate of an access transistor, wherein the gate material is deposited substantially above the metal line. In a second aspect, a semiconductor storage device, comprising: a first port to write data to a storage element; and a second port to read a signal generated by the storage element; and a first metal line coupled to a gate of an access transistor coupled to the first port; and a second metal line coupled to a gate of an access transistor coupled to the second port; wherein, the gates of said access transistors are formed on a gate material deposited substantially above the metal of first and second metal lines.

Claims

1. A semiconductor storage device, comprising:

a metal line coupled to a gate of an access transistor, wherein the gate material is deposited substantially above the metal line.

2. The device of claim 1, wherein the storage element comprises one or more elements selected from the following:

diode, transistor, resistor, capacitor, thin film diode, thin film resistor, thin film capacitor, thin film transistor (TFT).

3. The device of claim 1, wherein the access transistor is used to alter stored data in the device or read stored data from the device.

4. The device of claim 1, wherein the gate material is one of amorphous silicon, poly silicon, conductor material, semiconductor material, metal and refractory metal.

5. The device of claim 1, including a storage element wherein the access transistor is coupled to the storage element.

6. The device of claim 5, wherein the storage element is one of volatile and non volatile storage elements.

7. The device of claim 5, wherein the storage element is selected from a group of:

fuse links, latches, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, resistance modulating elements, optical elements, charge storage element, Carbon nano-tubes, voltage modulating element, and ferro-electric elements.

8. The device of claim 1, including an isolation circuit coupled to the storage element to generate a signal from the data stored in the storage element, the isolation circuit comprising one or more of:

diode, transistor, resistor, capacitor, thin film diode, thin film resistor, thin film capacitor, and thin film transistor (TFT).

9. The device of claim 1, including an isolation circuit coupled to the storage element to generate a signal from the data stored in the storage element, the isolation circuit comprising one or more of:

inverters, buffers, voltage converters, capacitors, resistors, and transistors.

10. The device of claim 1, including an isolation circuit coupled to the storage element to generate a signal from the data stored in the storage element, the isolation circuit including a node coupled to a programmable logic circuit to program the logic circuit.

11. An array of memory cells, comprising:

a plurality of storage elements, each element having an access transistor, said storage elements arranged in rows and columns in an array; and

a metal line coupled to a plurality of gates of the access transistors located in a said row of the array, wherein the access transistor gates are formed on a gate material deposited substantially above the metal line.

12. The device of claim 11, wherein each memory cell includes an isolation circuit comprising:

an input coupled to the storage element; and

a plurality of transistors capacitively coupled to the input; and

an output resistively coupled to two or more of said transistors, wherein the input is isolated from an output probe.

13. The device of claim 12, wherein the isolation circuit comprises one of:

buffer circuit, voltage modulation circuit, capacitor circuit, floating-gate circuit, inverter circuit, transistor circuit, thin-film transistor circuit, diode circuit and thin-film diode circuit.

14. The device of claim 12, wherein the output is coupled to a programmable logic circuit to program the logic circuit by altering the data state in the storage element.

15. The device of claim 12, wherein the output is coupled to a metal tab, said tab positioned substantially below the gate materials of the plurality of transistors.

16. The device of claim 11, wherein the storage element comprises a volatile or non volatile memory element.

17. The device of claim 11, wherein the storage element is selected from a group of:

fuse links, latches, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells,

18. The device of claim 14, wherein the logic element comprises one or more of:

pass gate logic, multiplexer logic, truth table logic, look up table logic, AND logic, NAND logic OR logic, NOR logic, arithmetic logic, carry logic, floating point logic, and any other logic.

19. A semiconductor storage device, comprising:

a first port to write data to a storage element; and

a second port to read a signal generated by the storage element; and

a first metal line coupled to a gate of an access transistor coupled to the first port; and

a second metal line coupled to a gate of an access transistor coupled to the second port;

wherein, the gates of said access transistors are formed on a gate material deposited substantially above the metal of first and second metal lines.

20. The device of claim 19, wherein the signal generated by the storage element is coupled to a programmable logic element to program the logic element.