Creating High Voltage FETs with Low Voltage Process
First Claim
1. A method of forming a high voltage first-conductivity type metal oxide semiconductor field effect transistor, comprising:
- forming one or more first-conductivity-well regions in an active area defined by an opening in field oxide over a second-conductivity-well, wherein the first-conductivity-well regions are formed to include first-conductivity−
drift capabilities;
forming a gate oxide region over the second-conductivity-well in the active area and a portion of the one or more first-conductivity-well regions; and
applying a plurality of spacers on opposing sides of the gate oxide region, wherein one or more spacers define an opening to the first-conductivity-well regions.
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Accused Products
Abstract
An integrated circuit (IC) includes a high voltage first-conductivity type field effect transistor (HV-first-conductivity FET) and a high voltage second-type field effect transistor (HV-second-conductivity FET). The HV first-conductivity FET has a second-conductivity-well and a field oxide formed over the second-conductivity-well to define an active area. A first-conductivity-well is formed in at least a portion of the active area, wherein the first-conductivity-well is formed to have the capability to operate as a first-conductivity− drift portion of the HV-first-conductivity FET. The HV second-conductivity FET has a first-conductivity-well and a field oxide formed over the first-conductivity-well to define an active area. A channel stop region I s formed in at least a portion of the active area, wherein the channel stop region is formed to have the capability to operate as second-conductivity− drift portions of the HV-second-conductivity FET.
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Citations
34 Claims
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1. A method of forming a high voltage first-conductivity type metal oxide semiconductor field effect transistor, comprising:
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forming one or more first-conductivity-well regions in an active area defined by an opening in field oxide over a second-conductivity-well, wherein the first-conductivity-well regions are formed to include first-conductivity−
drift capabilities;forming a gate oxide region over the second-conductivity-well in the active area and a portion of the one or more first-conductivity-well regions; and applying a plurality of spacers on opposing sides of the gate oxide region, wherein one or more spacers define an opening to the first-conductivity-well regions. - View Dependent Claims (2, 3)
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4. A method of forming a high voltage first-conductivity-type metal oxide semiconductor field effect transistor, comprising:
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forming one or more channel stop regions in an active area defined by an opening in field oxide over a second-conductivity-well, wherein the channel stop regions are formed to include first-conductivity−
drift capabilities; andforming a gate oxide region over the second-conductivity-well in the active area and a portion of one or more channel stop regions. - View Dependent Claims (5, 6, 7)
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8. A method of creating a high voltage (HV) first-conductivity FET with a low voltage (LV) process, comprising:
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modifying a first-conductivity-well mask to define first-conductivity−
drift regions to define a HV drain region in a second-conductivity-substrate during the definition of first-conductivity-wells in the LV process;modifying a second-conductivity-well mask to define a second-conductivity-well area adjacent to the HV drain region to create a HV gate region during the definition of the second-conductivity-wells in the LV process; creating a first gate oxide mask for the HV gate region and LV process for threshold adjust implants for the HV gate region and the LV process; and applying a first threshold adjust implant to the HV gate region and a second threshold adjust implant for the LV process. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method of creating a high voltage (HV) first-conductivity FET with a low voltage (LV) process, comprising:
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modifying a second-conductivity-well mask to define a HV second-conductivity-well for the HV-first-conductivity FET in a first-conductivity-substrate during the definition of second-conductivity-well in the LV process; defining an HV active area protective mask for the HV-first-conductivity FET during definition of the active area protective masks of the LV process; modifying a channel stop mask disposed on the active area protective masks to define a first-conductivity−
drift region in the HV active area;modifying the LV process channel stop implant step to create a sequential chain implant having at least one high energy implant sufficient to penetrate through active area protective mask to create the HV drain region in the defined first-conductivity−
drift region;creating a first gate oxide mask for a HV gate region and LV process for threshold adjust implants for the HV second-conductivity-well and the LV process; and applying a first threshold adjust implant to the HV second-conductivity-well and a second threshold adjust implant for the LV process. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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23. A method of creating a high voltage (HV) first-conductivity FET and a HV-second-conductivity FET with a low voltage (LV) process, comprising:
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modifying a first-conductivity-well mask to define first-conductivity−
drift regions to define a HV-first-conductivity FET drain region and a HV first-conductivity-well for the HV-second-conductivity FET in a substrate during the definition of first-conductivity-wells in the LV process;modifying a second-conductivity-well mask to define a second-conductivity-well area adjacent to the HV-first-conductivity FET drain region to create a HV-first-conductivity FET gate region during the definition of the second-conductivity-wells in the LV process; creating a first gate oxide mask for the HV-first-conductivity FET gate region, HV-second-conductivity FET gate region, and the LV process for threshold adjust implants; defining a HV active area protective mask for the HV-first-conductivity FET and the HV-second-conductivity FET during definition of the active area protective masks of the LV process; modifying a channel stop mask disposed on the active area protective masks to define a second-conductivity−
drift region in the HV-second-conductivity FET active area;modifying the LV process channel stop implant step to create a sequential chain implant having at least one high energy implant sufficient to penetrate through active area protective mask to create a HV-second-conductivity FET drain region in the defined second-conductivity−
drift region;applying a first threshold adjust implant to the HV-first-conductivity FET and the HV-second-conductivity FET gate regions and the HV first-conductivity-well; and applying a second threshold adjust implant for the LV process. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34-50. -50. (canceled)
Specification