Creating High Voltage FETs with Low Voltage Process

• US 20090130812A1
• Filed: 01/07/2009
• Published: 05/21/2009
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chen, Zhizhang, Huang, Chin, Hintzman, Jeff, Weaver, James
• Granted Patent: US 7,704,819 B2
• Time in Patent Office: Days
• US Class Current: 438/275
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An integrated circuit (IC) includes a high voltage first-conductivity type field effect transistor (HV-first-conductivity FET) and a high voltage second-type field effect transistor (HV-second-conductivity FET). The HV first-conductivity FET has a second-conductivity-well and a field oxide formed over the second-conductivity-well to define an active area. A first-conductivity-well is formed in at least a portion of the active area, wherein the first-conductivity-well is formed to have the capability to operate as a first-conductivity− drift portion of the HV-first-conductivity FET. The HV second-conductivity FET has a first-conductivity-well and a field oxide formed over the first-conductivity-well to define an active area. A channel stop region I s formed in at least a portion of the active area, wherein the channel stop region is formed to have the capability to operate as second-conductivity− drift portions of the HV-second-conductivity FET.

Claims

1. A method of forming a high voltage first-conductivity type metal oxide semiconductor field effect transistor, comprising:

forming one or more first-conductivity-well regions in an active area defined by an opening in field oxide over a second-conductivity-well, wherein the first-conductivity-well regions are formed to include first-conductivity−

drift capabilities;

forming a gate oxide region over the second-conductivity-well in the active area and a portion of the one or more first-conductivity-well regions; and

applying a plurality of spacers on opposing sides of the gate oxide region, wherein one or more spacers define an opening to the first-conductivity-well regions.

2. The method of claim 1, further comprising implanting first-conductivity+ dopant in the one or more openings of the spacers.

3. The method of claim 1, further comprising:

forming first-conductivity+ source regions in the active area of the second-conductivity-well, wherein the first-conductivity+ source regions are formed to span from beneath the gate oxide to an edge of the active area.

4. A method of forming a high voltage first-conductivity-type metal oxide semiconductor field effect transistor, comprising:

forming one or more channel stop regions in an active area defined by an opening in field oxide over a second-conductivity-well, wherein the channel stop regions are formed to include first-conductivity−

drift capabilities; and

forming a gate oxide region over the second-conductivity-well in the active area and a portion of one or more channel stop regions.

5. The method of claim 4, further comprising:

applying a plurality of spacers on opposing sides of the gate oxide region, wherein one or more spacers define an opening to the channel stop regions; and

implanting first-conductivity+ dopant in the one or more openings of the spacers.

6. The method of claim 4, and further comprising:

forming first-conductivity+ source regions in the active area of the second-conductivity-well, wherein the first-conductivity+ source regions are formed to span from beneath the gate oxide to an edge of the active area.

7. The method of claim 4 wherein the step of forming one or more channel stop regions further comprises performing a sequential chain implant of high energy to lower energy dose implants.

8. A method of creating a high voltage (HV) first-conductivity FET with a low voltage (LV) process, comprising:

modifying a first-conductivity-well mask to define first-conductivity−

drift regions to define a HV drain region in a second-conductivity-substrate during the definition of first-conductivity-wells in the LV process;

modifying a second-conductivity-well mask to define a second-conductivity-well area adjacent to the HV drain region to create a HV gate region during the definition of the second-conductivity-wells in the LV process;

creating a first gate oxide mask for the HV gate region and LV process for threshold adjust implants for the HV gate region and the LV process; and

applying a first threshold adjust implant to the HV gate region and a second threshold adjust implant for the LV process.

9. The method of claim 8 wherein a HV source region is created using the same steps as creating the HV drain region to create a symmetric HV-first-conductivity FET.

10. The method of claim 8 wherein the LV process is used to create at least one of a set of LV first-conductivity FET and a set of LV second-conductivity FET transistors.

11. The method of claim 8, further comprising:

removing the first gate oxide mask for the LV process and not the HV gate region;

creating a second gate oxide mask for the LV process and the HV gate region; and

applying a low density diffusion implant for the LV process and not the HV drain region.

12. The method of claim 11, further comprising:

applying a spacer to the LV process and the HV-first-conductivity FET wherein the spacer region of the HV-first-conductivity FET spans the HV drain region and a portion of the HV gate region and defines an opening over the HV drain region; and

implanting a first-conductivity+ implant in the opening over the HV drain region during the first-conductivity+ implant of the LV process.

13. The method of claim 8 wherein a HV source region is created by extending the second-conductivity-well area used to create the HV gate region and applying the low density diffusion implant in the HV source region before implanting the HV source region with a first-conductivity+ implant to create an asymmetric HV-first-conductivity FET.

14. A method of creating a high voltage (HV) first-conductivity FET with a low voltage (LV) process, comprising:

modifying a second-conductivity-well mask to define a HV second-conductivity-well for the HV-first-conductivity FET in a first-conductivity-substrate during the definition of second-conductivity-well in the LV process;

defining an HV active area protective mask for the HV-first-conductivity FET during definition of the active area protective masks of the LV process;

modifying a channel stop mask disposed on the active area protective masks to define a first-conductivity−

drift region in the HV active area;

modifying the LV process channel stop implant step to create a sequential chain implant having at least one high energy implant sufficient to penetrate through active area protective mask to create the HV drain region in the defined first-conductivity−

drift region;

creating a first gate oxide mask for a HV gate region and LV process for threshold adjust implants for the HV second-conductivity-well and the LV process; and

applying a first threshold adjust implant to the HV second-conductivity-well and a second threshold adjust implant for the LV process.

15. The method of claim 14 wherein a HV source region is created using the same steps as creating the HV drain region to create a symmetric HV-first-conductivity FET.

16. The method of claim 14 wherein the LV process is used to create at least one of a set of LV first-conductivity FET and a set of LV second-conductivity FET transistors.

17. The method of claim 14, further comprising:

removing the first gate oxide mask for the LV process and not the HV gate region;

creating a second gate oxide mask for the LV process and the HV gate region; and

applying a low density diffusion implant for the LV process and not the HV drain region.

18. The method of claim 17, further comprising:

applying a spacer to the LV process and the HV-first-conductivity FET wherein the spacer region of the HV-first-conductivity FET spans a HV drain region and a portion of the HV gate region and defines an opening over the HV drain region; and

implanting a first-conductivity+ implant in the opening over the HV drain region during the first-conductivity+ implant of the LV process.

19. The method of claim 14 wherein a HV source region is created by not defining the HV source region with the modified channel stop mask thereby extending the first-conductivity-well area used to create the HV gate region and implanting the HV source region with a first-conductivity+ implant to create an asymmetric HV-second-conductivity FET.

20. The method of claim 14 wherein the sequential chain implant includes at least two high energy implants able to at least partially penetrate the active area protective mask to form a degraded lightly-doped first-conductivity−

drift region and one low energy implant blocked by the active area protective mask.

21. The method of claim 14 wherein the sequential chain implant includes at least three high energy implants of decreasing energy levels able to at least partially penetrate the active area protective mask to form a degraded lightly-doped first-conductivity−

drift region and a low energy implant blocked by the active area protective mask.

22. The method of claim 14 wherein the sequential chain implant includes at least one high energy implant able to at least partially penetrate the active area protective mask to form a degraded lightly-doped first-conductivity−

drift region before performing a channel stop implant of the LV process.

23. A method of creating a high voltage (HV) first-conductivity FET and a HV-second-conductivity FET with a low voltage (LV) process, comprising:

modifying a first-conductivity-well mask to define first-conductivity−

drift regions to define a HV-first-conductivity FET drain region and a HV first-conductivity-well for the HV-second-conductivity FET in a substrate during the definition of first-conductivity-wells in the LV process;

modifying a second-conductivity-well mask to define a second-conductivity-well area adjacent to the HV-first-conductivity FET drain region to create a HV-first-conductivity FET gate region during the definition of the second-conductivity-wells in the LV process;

creating a first gate oxide mask for the HV-first-conductivity FET gate region, HV-second-conductivity FET gate region, and the LV process for threshold adjust implants;

defining a HV active area protective mask for the HV-first-conductivity FET and the HV-second-conductivity FET during definition of the active area protective masks of the LV process;

modifying a channel stop mask disposed on the active area protective masks to define a second-conductivity−

drift region in the HV-second-conductivity FET active area;

modifying the LV process channel stop implant step to create a sequential chain implant having at least one high energy implant sufficient to penetrate through active area protective mask to create a HV-second-conductivity FET drain region in the defined second-conductivity−

drift region;

applying a first threshold adjust implant to the HV-first-conductivity FET and the HV-second-conductivity FET gate regions and the HV first-conductivity-well; and

applying a second threshold adjust implant for the LV process.

24. The method of claim 23 wherein a HV-first-conductivity FET source region is created using the same steps as creating the HV-first-conductivity FET drain region to create a symmetric HV-first-conductivity FET.

25. The method of claim 23 wherein the LV process is used to create at least one of a set of LV first-conductivity FET and a set of LV second-conductivity FET transistors.

26. The method of claim 23, further comprising:

removing the first gate oxide mask for the LV process and not the HV-first-conductivity FET and HV-second-conductivity FET gate regions;

creating a second gate oxide mask for the LV process and the HV-first-conductivity FET and HV-second-conductivity FET gate regions; and

applying a low density diffusion implant for the LV process and not the HV-first-conductivity FET and HV-second-conductivity FET drain regions.

27. The method of claim 26, further comprising:

applying a spacer to the LV process and the HV-first-conductivity FET and the HV-second-conductivity FET wherein the spacer regions of the HV-first-conductivity FET and the HV-second-conductivity FET spans the HV drain regions and a portion of the HV gate regions and defines a set of openings over the HV drain regions;

implanting a first-conductivity+ implant in the set of openings over the HV-first-conductivity FET drain regions during the first-conductivity+ implant of the LV process; and

implanting a second-conductivity+ implant in the set of openings over the HV-second-conductivity FET drain regions during the second-conductivity+ implant of the LV process.

28. The method of claim 23 wherein a HV-first-conductivity FET source region is created by extending the second-conductivity-well area used to create the HV-first-conductivity FET gate region and applying the low density diffusion implant in the HV-first-conductivity FET source region before implanting the HV-first-conductivity FET source region with a first-conductivity+ implant to create an asymmetric HV-first-conductivity FET.

29. The method of claim 23 wherein a HV-second-conductivity FET source region is created using the same steps as creating the HV-second-conductivity FET drain region to create a symmetric HV-second-conductivity FET.

30. The method of claim 23 wherein a HV-second-conductivity FET source region is created by not defining the HV-second-conductivity FET source region with the modified channel stop mask thereby extending the second-conductivity-well area used to create the HV-second-conductivity FET gate region and implanting the HV-second-conductivity FET source region with a second-conductivity+ implant to create an asymmetric HV-second-conductivity FET.

31. The method of claim 23 wherein the sequential chain implant includes at least two high energy implants able to at least partially penetrate the active area protective mask to form a degraded lightly-doped second-conductivity−

drift region and one low energy implant blocked by the active area protective mask.

32. The method of claim 23 wherein the sequential chain implant includes at least three high energy implants of decreasing energy levels able to at least partially penetrate the active area protective mask to form a degraded lightly-doped second-conductivity−

drift region and a low energy implant blocked by the active area protective mask.

33. The method of claim 23 wherein the sequential chain implant includes at least one high energy implant able to at least partially penetrate the active area protective mask to form a degraded lightly-doped second-conductivity−

drift region before performing the normal channel stop implant of the LV process.

34-50. -50. (canceled)