RECEIVED COMMUNICATION SIGNAL PROCESSING METHODS AND COMPONENTS FOR WIRELESS COMMUNICATION EQUIPMENT

• US 20090131009A1
• Filed: 10/03/2008
• Published: 05/21/2009
• Est. Priority Date: 03/05/2003
• Status: Abandoned Application

• Current Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Original Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Inventors: Meyer, Jan, Bohnhoff, Peter, Ferrante, Steven, Reznik, Alexander, Hepler, Edward L., Hackett, William C.
• Application Number:
  US12/245,164
• Publication Number:
  US 20090131009A1
• Time in Patent Office: Days
• US Class Current: 455/334
• CPC Class Codes: H04B 1/70735 Code identification H04B1/7083 takes precedence
• CPC Class Codes: H04B 1/70755 Setting of lock conditions, e.g. threshold
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/7083 Cell search, e.g. using a three-step approach
• CPC Class Codes: H04B 1/7113 Determination of path profile
• CPC Class Codes: H04B 1/7117 Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
• CPC Class Codes: H04B 17/364 Delay profiles
• CPC Class Codes: H04B 7/08 at the receiving station
• CPC Class Codes: H04J 13/10 Code generation
• CPC Class Codes: H04L 25/0212 of impulse response

Abstract

A wireless transmit receive unit (WTRU) and methods are used in a wireless communication system to process sampled received signals to establish and/or maintain wireless communications. A selectively controllable coherent accumulation unit produces power delay profiles (PDPs). A selectively controllable post processing unit passes threshold qualified magnitude approximation values and PDP positions to a device such as a rake receiver to determine receive signal paths.

Claims

1. A wireless transmit receive unit (WTRU) for use in wireless communications comprising:

an antenna system for receiving wireless signals and producing at least one sequential stream of received signal samples at a selected sampling rate;

a sequential array of N vector correlators VC [1] to VC [N], each configured for coherently accumulating sets of sequential received signal samples;

a sequence generator configured to selectively generate known sequences sought to be detected in received wireless signals;

the vector correlators coupled with the antenna system and the sequence generator such that for a series of a predetermined length of samples, the vector correlators process respective successive sets of samples which collectively include all samples in the series with a generated known sequence to produce mixed values that are coherently accumulated in the vector correlators; and

vector correlator accumulator control circuitry configured to selectively control an accumulated mixed value output of each vector correlator such that each vector correlator outputs an accumulated value after accumulating a selected number of sets of accumulated mixed values whereby power delay profiles (PDPs) of a series of at least N elements E₁ to E_N are produced.

2. The WTRU of claim 1 wherein the vector correlator accumulator control circuitry is configured to selectively control an accumulated mixed value output of each vector correlator such that each vector correlator outputs a selected number P of accumulated values whereby power delay profiles (PDPs) of a series of N*P elements are produced.

3. The WTRU of claim 1 wherein:

the antenna system is configured with multiple antennas to produce multiple sequential streams of received signal samples at the selected sampling rate, and

the vector correlators each include a controllable antenna switch device configured to select a sample stream from among the multiple sample streams.

4. The WTRU of claim 3 wherein the array of vector correlators includes antenna switch control circuitry configured to control the antenna switch devices such that for any given series of a predetermined length of samples, the antenna switch devices are controlled to select a particular sample stream for each of the respective vector correlators to process respective successive sets of samples which collectively include all samples in the series.

5. The WTRU of claim 1 wherein each vector correlator is configured with a plurality of n accumulator devices such that each accumulator device is coupled to the sequence generator to receive elements of a generated known sequence for mixing with signal samples processed by the vector correlator such that each sample can be processed with n different generated known sequences to produce n accumulations of mixed values whereby the vector correlator array can concurrently produce n PDPs, each corresponding to one of the n different generated known sequences.

6. The WTRU of claim 1 wherein:

the sequence generator includes a scrambling code generator and n signature code generators such that the sequence generator outputs n different signature and scrambling code combination sequences of generated elements; and

each vector correlator is configured with a plurality of n accumulator devices such that each accumulator device is coupled to the sequence generator to receive elements of a generated sequence for mixing with signal samples processed by the vector correlator such that each sample can be processed with n different sequences to produce n accumulations of mixed values whereby the vector correlator array can concurrently produce n PDPs, each corresponding to one of the n different sequences.

7. The WTRU of claim 1 wherein hardware devices in the vector correlators are configured to operate at least twice the selected sampling rate and the vector correlators process respective successive sets of samples with odd elements of the generated known sequence and, after a delay of N even elements of the generated known sequence, with even elements of the generated known sequence to produce double the number of mixed values that are coherently accumulated in the vector correlators.

8. The WTRU of claim 1 wherein the array of vector correlators operates at a speed that is 48 times faster than the selected sampling rate.

9. The WTRU of claim 1 further comprising:

an interpolator coupled with the vector correlators and configured to produce expanded PDPs by increasing the number of PDP elements by a desired multiple through interpolation; and

a post processing unit for processing the expanded PDPs that includes;

a magnitude approximation device configured to provide magnitude approximation values of expanded PDP values; and

a threshold evaluation device;

the post processing device configured to pass magnitude approximation values and associated PDP position values that are qualified by the threshold evaluation device to a RAKE receiver.

10. The WTRU of claim 8 configured for use as a Node B in a Universal Mobile Telecommunications System (UMTS).

11. The WTRU of claim 8 configured for use as a User Equipment (UE) in a Universal Mobile Telecommunications System (UMTS).

12. A method for processing received wireless signals comprising:

producing at least one sequential stream of received signal samples at a selected rate;

selectively generating known sequences sought to be detected in received wireless signals;

coherently accumulating sets of sequential received signal samples using a sequential array of N vector correlators VC[1] to VC[N] such that for a series of a predetermined length of samples, the vector correlators process respective successive sets of samples which collectively include all samples in the series with a generated known sequence to produce mixed values that are coherently accumulated in the vector correlators; and

selectively controlling an accumulated mixed value output of each vector correlator such that each vector correlator outputs an accumulated value after accumulating a selected number of sets of accumulated mixed values whereby power delay profiles (PDPs) of a series of at least N elements E₁ to E_N are produced.

13. The method of claim 12 wherein the vector correlators are selectively controlled such that each vector correlator outputs a selected number P of accumulated values whereby power delay profiles (PDPs) of a series of N*P elements are produced.

14. The method of claim 12 wherein multiple sequential streams of received signal samples at the selected rate are produced, and

a sample stream from among the multiple sample streams is selected.

15. The method of claim 14 wherein the sample stream selection is controlled that for any given series of a predetermined length of samples, the vector correlators are controlled to select a particular sample stream to process respective successive sets of samples which collectively include all samples in the series.

16. The method of claim 12 where each vector correlator is configured with a plurality of n accumulator devices wherein during the coherent accumulation, each accumulator device of a vector correlator receives elements of a generated known sequence for mixing with signal samples processed by the vector correlator such that each sample can be processed with n different generated known sequences to produce n accumulations of mixed values whereby the coherent accumulation can concurrently produce n PDPs, each corresponding to one of the n different generated known sequences.

17. The method of claim 16 wherein:

the sequence generating includes generating a scrambling code and n signature codes and outputting in parallel n sequences such that each sequence is a different signature code and scrambling code combination of generated elements; and

during the coherent accumulation, each accumulator device of a vector correlator receives elements of a generated sequence for mixing with signal samples processed by the vector correlator such that each sample is processed with n different sequences to produce n accumulations of mixed values where by n PDPs are concurrently produced, each corresponding to one of the n different sequences.

18. The method of claim 12, wherein coherent accumulation is performed at at least twice the selected sampling rate and the vector correlators process respective successive sets of samples with odd elements of the generated known sequence and, after a delay of N even elements of the generated known sequence, with even elements of the generated known sequence to produce double the number of mixed values that are coherently accumulated in the vector correlators.

19. The method of claim 12 wherein the coherent accumulation is performed at a speed that is 48 times faster than the selected sampling rate.

20. The method of claim 12 further comprising:

producing expanded PDPs by increasing the number of PDP elements by a desired multiple through interpolation; and

processing the expanded PDPs, including producing magnitude approximation values of expanded PDP values, such that magnitude approximation values and associated PDP position values that are qualified by a threshold device are passed to a RAKE receiver.