SYSTEM AND METHOD FOR RECOVERING FROM TRANSIENT FAULTS IN AN IMPLANTABLE MEDICAL DEVICE

• US 20090132061A1
• Filed: 01/26/2009
• Published: 05/21/2009
• Est. Priority Date: 05/05/2005
• Status: Active Grant

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Hoyme, Kenneth P., Linder, William J., Elliott, Lynn S., Doshi, Hiten J., Stubbs, Scott, Sowder, Conrad L.
• Granted Patent: US 8,170,670 B2
• Time in Patent Office: Days
• US Class Current: 700/8
• CPC Class Codes: A61N 1/3706 Pacemaker parameters stimulation threshold A61N1/371

Abstract

A system and method is disclosed for system fault recovery by an implantable medical device which employs a global fault response. The system enables the device to consistently recover from transient faults while maintaining a history of the reason for the device fault. Upon detection of a fault, the primary controller of the device signals a reset controller which then issues a reset command. All sub-systems of the primary device controller are then reset together rather than resetting individual sub-systems independently to ensure deterministic behavior.

Claims

1. A method for operating an implantable medical device, comprising:

controlling the operation of the device with a primary controller;

detecting faults with fault monitoring circuitry;

upon detection of a fault by the fault monitoring circuitry, signaling the primary controller to halt operation and to activate a fail-safe subsystem for delivering therapy;

after activation of the fail-safe subsystem, signaling the primary controller to validate its operation with a self-test and to deactivate the fail-safe subsystem if the primary controller is validated; and

,

employing a system-reset monitor to detect system resets caused by non-recoverable and persistent faults and to maintain a reset count that is incremented when an internal reset generated by the fault monitoring circuitry occurs, wherein the reset count is intermittently decremented.

2. The method of claim 1 further comprising employing a watchdog timer.

3. The method of claim 1 further comprising monitoring clock deviation.

4. The method of claim 1 wherein the detecting of faults includes detecting memory errors.

5. The method of claim 1 further comprising, upon detection of a fault, signaling the primary controller to initiate logging of possible causes of the fault.

6. The method of claim 5 further comprising providing an input signifying a fault event to a reset controller when a fault is detected by either the primary controller or the fault monitoring circuit.

7. The method of claim 1 further comprising, upon detection of a fault, providing a pending reset signal to initiate logging of the cause of the pending reset by the primary controller.

8. The method of claim 1 wherein the reset count is decremented by one count after expiration of a specified time period until the reset count is zero.

9. The method of claim 1 further comprising detecting a non-recoverable or persistent fault when a specified number of internal resets occur within the specified time period such that a system-reset monitor inhibits further attempts to restart the primary system and allows the fail-safe backup system to maintain therapy indefinitely without interruption.

10. The method of claim 1 further comprising logging recent resets in a FIFO buffer.

11. The method of claim 1 further comprising disabling the system-reset monitor once it has tripped to prevent subsequent internal resets from overwriting data and re-enabling the system-reset monitor with an external reset.

12. A method for operating an implantable medical device, comprising:

controlling the operation of the device with a primary controller;

detecting faults with fault monitoring circuitry;

upon detection of a fault by the fault monitoring circuitry, signaling the primary controller to halt operation and to activate a fail-safe subsystem for delivering therapy;

after activation of the fail-safe subsystem, signaling the primary controller to validate its operation with a self-test and to deactivate the fail-safe subsystem if the primary controller is validated; and

,

monitoring program behavior in the primary controller by detecting extended thread execution time and thread sequence anomalies, wherein a thread is defined as one of several paths of execution inside a single process or context.

13. The method of claim 12 further comprising allocating to each thread an identifier ID and a time limit in processor cycles at compile time, which information is used to configure the thread monitor at the beginning of the thread execution.

14. The method of claim 12 further comprising providing a thread start signal which includes the thread'"'"'s ID and time limit that is stored in a thread monitor when a thread is started.

15. The method of claim 14 further comprising providing a thread stop signal which also includes the thread'"'"'s ID when execution of the thread has completed.

16. The method of claim 15 further comprising a reset request signal that is raised if the thread stop signal is not received before the time limit expires or if the start and stop ID'"'"'s are mismatched.

17. The method of claim 16 further comprising providing a reset request signal that is raised if the start and stop ID'"'"'s are mismatched.

18. The method of claim 17 further comprising returning the most recent start ID, stop ID, time limit, and remaining time in response to a status signal received from system software in order to provide a context to allow thread interruption.