STRIPED ON-CHIP INDUCTOR
First Claim
1. A sub-100 nanometer process semiconductor inductor comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and connecting a first inductor port to a second inductor port;
- the lines each having a width and a cross-sectional area, each line spaced from an adjacent line by a spacing gap;
wherein the plurality of line widths, cross-sectional areas and spacing gaps are a function of Design Rule Check rules comprising a Chemical Mechanical Planarization metal ratio rule, and the plurality of line widths, cross-sectional areas and spacing gaps formed to comply with the Chemical Mechanical Planarization metal ratio rule.
5 Assignments
0 Petitions
Accused Products
Abstract
Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
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Citations
12 Claims
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1. A sub-100 nanometer process semiconductor inductor comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and connecting a first inductor port to a second inductor port;
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the lines each having a width and a cross-sectional area, each line spaced from an adjacent line by a spacing gap; wherein the plurality of line widths, cross-sectional areas and spacing gaps are a function of Design Rule Check rules comprising a Chemical Mechanical Planarization metal ratio rule, and the plurality of line widths, cross-sectional areas and spacing gaps formed to comply with the Chemical Mechanical Planarization metal ratio rule. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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producing computer executable program code; storing the produced program code on a computer readable medium; and providing the program code to be deployed to and executed on a computer system; the program code comprising instructions which, when executed on the computer system, causes the computer system to; use an Electronic Design Automation tool to determine sub-100 nanometer process metal line height, width and line spacing dimensions as a function of Design Rule Check rules comprising a Chemical Mechanical Planarization metal ratio rule; and cause process equipment to form a plurality of spaced parallel metal lines on a dielectric substrate between first and second ports according to the determined height, width and line spacing dimensions to comply with the Chemical Mechanical Planarization metal ratio rule. - View Dependent Claims (10)
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11. A method for deploying an application for forming a semiconductor inductor, comprising:
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providing a computer infrastructure being operable to; determine sub-100 nanometer process metal line height, width and line spacing dimensions as a function of Design Rule Check rules comprising a Chemical Mechanical Planarization metal ratio rule; and cause process equipment to form a plurality of spaced parallel metal lines on a substrate according to the determined height, width and line spacing dimensions, the plurality of line height, width and line spacing dimensions formed to comply with the Chemical Mechanical Planarization metal ratio rule. - View Dependent Claims (12)
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Specification