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STRIPED ON-CHIP INDUCTOR

  • US 20090132082A1
  • Filed: 01/30/2009
  • Published: 05/21/2009
  • Est. Priority Date: 09/29/2006
  • Status: Active Grant
First Claim
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1. A sub-100 nanometer process semiconductor inductor comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and connecting a first inductor port to a second inductor port;

  • the lines each having a width and a cross-sectional area, each line spaced from an adjacent line by a spacing gap;

    wherein the plurality of line widths, cross-sectional areas and spacing gaps are a function of Design Rule Check rules comprising a Chemical Mechanical Planarization metal ratio rule, and the plurality of line widths, cross-sectional areas and spacing gaps formed to comply with the Chemical Mechanical Planarization metal ratio rule.

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