POWER CONSERVATION VIA DRAM ACCESS

• US 20090132764A1
• Filed: 11/13/2006
• Published: 05/21/2009
• Est. Priority Date: 11/15/2005
• Status: Active Grant

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation), Sun Microsystems Technology Ltd. (Oracle Corporation)
• Original Assignee: Montalvo Systems, Inc. (Oracle Corporation)
• Inventors: GLASKOWSKY, Peter N., MOLL, Laurent R., CHENG, Yu Qing, SONG, Seungyoon Peter
• Granted Patent: US 7,899,990 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.

Claims

1. A method comprising:

storing at least a portion of non-cacheable data in a cache associated with a microprocessor configured to operate in a buffer mode.

2. The method of claim 1, wherein the non-cacheable data is display refresh data (DRD).

3. The method of claim 1 wherein the buffer mode comprises allowing the microprocessor to operate in a low power state.

4. The method of claim 1 wherein the storing comprises utilizing lower limit and upper limit registers to specify the at least a portion of the non-cacheable data to match the cache size.

5. The method of claim 1 wherein the storing comprises utilizing a base register and an offset limit register to specify the at least a portion of the non-cacheable data such that its size matches to the cache size.

6. The method of claim 1 wherein the storing comprises utilizing at least one request property for identifying a source of the non-cacheable data.

7. The method of claim 1 wherein a direct mapped policy is utilized in the buffer mode.

8. The method of claim 1 wherein the storing is initiated by a normal mode to buffer mode event.

9. The method of claim 1 wherein the normal mode to buffer mode event comprises the microprocessor being in a reduced power state.

10. The method of claim 1 wherein the non-cacheable data is stored in the cache such that the amount of non-cacheable data never exceeds the cache size.

11. A microprocessor system comprising:

a processor; and

a cache system, the cache system comprising a cache and a controller coupled to the cache, the controller configured to store at least a portion of non-cacheable data in the cache, when the microprocessor operates in the buffer mode.

12. The microprocessor of claim 11, wherein the non-cacheable data is display refresh data (DRD).

13. The microprocessor of claim 11 wherein the buffer mode comprises allowing the microprocessor system to operate in a low power state.

14. The microprocessor of claim 11 wherein the controller is further configured to use a lower limit register and an upper limit register to specify the at least a portion of the non-cacheable data.

15. The microprocessor of claim 11 wherein the controller is further configured to use a base register and an offset limit register to specify the at least a portion of the non-cacheable data to match the cache size.

16. The microprocessor of claim 11 wherein storing comprises utilizing at least one request property for identifying a source of the non-cacheable data.

17. The microprocessor of claim 11 wherein the controller is further configured to use a direct mapped policy when the microprocessor is in the buffer more.

18. The microprocessor of claim 11 wherein a normal mode to buffer mode event initiates storing by the controller, at least a portion of non-cacheable data in the cache.

19. The microprocessor of claim 11 wherein the normal mode to buffer mode event comprises the microprocessor being in a reduced power state.

20. The microprocessor of claim 11 wherein the controller is further configured to store non-cacheable data in the cache such that the amount of non-cacheable data never exceeds the cache size.

21. A computer readable medium containing program instructions for:

storing at least a portion of non-cacheable data in a cache associated with a microprocessor configured to operate in a buffer mode.

22. A medium readable by a computer system that contains descriptions that generate, when interpreted by the computer system, a circuit comprising:

storing at least a portion of non-cacheable data in a cache associated with a microprocessor configured to operate in a buffer mode.