SYSTEM, METHOD AND A COMPUTER PROGRAM PRODUCT FOR WRITING DATA TO DIFFERENT STORAGE DEVICES BASED ON WRITE FREQUENCY

• US 20090132778A1
• Filed: 11/19/2007
• Published: 05/21/2009
• Est. Priority Date: 11/19/2007
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: SandForce, Inc. (Broadcom, Inc.)
• Inventors: Danilak, Radoslav
• Granted Patent: US 7,849,275 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A system, method, and computer program product are provided for writing data to different storage devices based on write frequency. In operation, a frequency in which data is written is identified. Additionally, a plurality of storage devices of different types is selected from to write the data, based on the frequency.

Claims

1. A method, comprising:

identifying a frequency in which data is written; and

selecting from a plurality of storage devices of different types to write the data, based on the frequency.

2. The method of claim 1, wherein the selecting is further based on a threshold.

3. The method of claim 1, and further comprising determining a threshold.

4. The method of claim 3, wherein the data is written to a storage device of a first type if the frequency exceeds the threshold.

5. The method of claim 4, wherein the first type of storage device includes a single-level cell (SLC) storage device.

6. The method of claim 4, wherein the data is written to a storage device of a second type if the frequency does not exceed the threshold.

7. The method of claim 4, wherein the first type of storage device includes a multi-level cell (MLC) storage device.

8. The method of claim 1, wherein the frequency is monitored by a lifetime estimator module.

9. The method of claim 8, wherein the lifetime estimator module computes an estimated lifetime of the storage devices.

10. The method of claim 8, wherein the lifetime estimator module computes an estimated lifetime of the storage devices, based on storage commands.

11. The method of claim 1, wherein the storage devices include a mechanical storage device.

12. The method of claim 11, wherein the mechanical storage device includes a disk drive.

13. The method of claim 1, wherein the storage devices include a solid state storage device.

14. The method of claim 13, wherein the solid state storage device includes flash memory.

15. The method of claim 14, wherein the flash memory includes NAND flash memory.

16. The method of claim 1, wherein at least one of the storage devices includes single-level cell (SLC) flash memory and multi-level cell (MLC) flash memory on the same storage device.

17. The method of claim 16, and further comprising determining a portion of the at least one storage device associated with the single-level cell (SLC) flash memory and a portion of the at least one storage device associated with the multi-level cell (MLC) flash memory.

18. The method of claim 1, wherein at least one of the storage devices includes two different types of single-level cell (SLC) flash memory devices on the same storage device.

19. The method of claim 1, wherein the storage devices include volatile memory.

20. The method of claim 1, wherein the storage devices include non-volatile memory.

21. A computer program product embodied on a computer readable medium, comprising:

computer code for identifying a frequency in which data is written; and

selecting from a plurality of storage devices of different types to write the data, based on the frequency.

22. An apparatus, comprising:

a circuit for identifying a frequency in which data is written, and selecting from a plurality of storage devices of different types to write the data, based on the frequency.

23. The apparatus of claim 22, wherein the circuit is coupled between a system and memory.