Hardware-error tolerant computing

• US 20090132853A1
• Filed: 01/08/2009
• Published: 05/21/2009
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: Searete LLC (Intellectual Ventures LLC)
• Inventors: Mangione-Smith, William Henry, Myhrvold, Nathan P., Tegreene, Clarence T., Hillis, W. Daniel, Ferren, Bran, Wood, Lowell L. JR.
• Granted Patent: US 8,255,745 B2
• Time in Patent Office: Days
• US Class Current: 714/19
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream

Abstract

Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an information store operable to save a sequence of instructions. The computing system further includes a controller module. The controller module includes a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem. The controller further includes a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.

Claims

1. A computing system comprising:

a processor subsystem having an adjustable physical operating parameter;

an information store operable to save a sequence of instructions; and

a controller module including;

a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and

a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion.

2. The computing system of claim 1, wherein the controller module including a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem includes:

a controller module including a monitor circuit for detecting an incidence of a computational error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.

3. The computing system of claim 1, wherein the controller module including a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem includes:

a controller module including a monitor circuit for detecting an incidence of an execution path synchronization error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.

4. The computing system of claim 1, wherein the controller module including a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem includes:

a controller module including a hardware-implemented monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.

5. The computing system of claim 1, wherein the controller module including a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem includes:

a controller module including a monitor circuit implemented in at least one of hardware, software, firmware, and/or a microengine for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.

6. The computing system of claim 1, wherein the controller module including a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem includes:

a controller module including a monitor circuit implemented in a dynamic implementation verification architecture (DIVA) and for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.

7. The computing system of claim 1, wherein the controller module including a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem includes:

a controller module including a monitor circuit employing a TEATime execution checker algorithm and for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.

8. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including control circuit implemented in at least one of hardware, software, firmware, and/or a microengine and for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion.

9. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including control circuit implemented in software associated with at least one of an operating system and/or a program executable by the processor subsystem and for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion.

10. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including a control circuit for at least one of initiating, activating, causing, facilitating, accomplishing, and/or achieving an adjustment of the adjustable physical operating parameter based upon an error-tolerant performance criterion.

11. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including a control circuit for adjusting a voltage of the processor subsystem based upon an error-tolerant performance criterion.

12. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including a control circuit for adjusting a frequency of a timing signal employed by the processor subsystem based upon an error-tolerant performance criterion.

13. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including a control circuit for adjusting a processor clock based upon an error-tolerant performance criterion.

14. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including a control circuit for adjusting the adjustable physical operating parameter to substantially minimize a time required to successfully complete an execution of the sequence of instructions.

16. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including a control circuit for adjusting the adjustable physical operating parameter to substantially minimize a time to complete an execution of the sequence of instructions.

17. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including a control circuit for adjusting a processor clock frequency to substantially minimize a time to complete an execution of the sequence of instructions.

24. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including a control circuit for adjusting a processor clock frequency to substantially minimize an expected time to successfully complete an execution of the sequence of instructions while at least one other adjustable physical operating parameter remains substantially constant.

25. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant dynamically-derived performance criterion.

26. The computing system of claim 25, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant dynamically-derived performance criterion includes:

a controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant dynamically-derived performance criterion having an objective to substantially minimize an expected time to successfully complete an execution of the sequence of instruction.

27. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an empirically-based error-tolerant performance map.

28. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including a control circuit for adjusting the adjustable physical operating parameter based upon a performance criterion embodied in a lookup table.

29. The computing system of claim 28, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon a performance criterion embodied in a lookup table includes:

a controller module including a control circuit for adjusting the adjustable physical operating parameter based upon a performance criterion embodied in a lookup table and having an objective of substantially minimizing a time to complete an execution of the sequence of instruction.

30. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion includes:

a controller module including a control circuit for adjusting the adjustable physical operating parameter based upon an error-tolerant performance criterion corresponding to an incidence of the detected operating-parameter-caused error.

31. The computing system of claim 1, wherein the controller module includes an error recovery circuit operable to restore an execution of the sequence of program instructions to a checkpoint based upon the detected operating-parameter-caused error.

45. The computing system of claim 1, wherein the adjustable physical operating parameter includes:

an adjustable electrical operating parameter.

46. The computing system of claim 1, wherein the adjustable physical operating parameter includes:

an adjustable thermal operating parameter.

15. (canceled)

18-23. -23. (canceled)

32. A method implemented in a computerized system, the method comprising:

detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable physical operating parameter; and

changing the adjustable processor physical operating parameter based upon an error-tolerant performance criterion.

33. The method of claim 32, wherein the detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable physical operating parameter includes:

detecting an incidence of a setup/hold violation corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable physical operating parameter.

34. The method of claim 32, wherein the detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable physical operating parameter includes:

detecting an incidence of an execution path synchronization error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable physical operating parameter.

35. The method of claim 32, wherein the detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable physical operating parameter includes:

detecting an incidence of at least one of a single incidence, an incidence frequency, an incidence occurrence rate, an incidence tempo, an incidence pattern, or an incidence prevalence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable physical operating parameter.

36. The method of claim 32, wherein the changing the adjustable processor physical operating parameter based upon an error-tolerant performance criterion includes:

changing the adjustable processor physical operating parameter based upon an error-tolerant performance criterion to substantially minimize a time required to successfully complete an execution of the sequence of instructions.

38. The method of claim 36, wherein the changing the adjustable processor physical operating parameter based upon an error-tolerant performance criterion to substantially minimize a time required to successfully complete an execution of the sequence of instructions includes

changing the adjustable processor physical operating parameter based upon an error-tolerant and dynamically-derived performance criterion having an objective to substantially minimize a time to execute the sequence of instruction by the processor subsystem.

41. The method of claim 32, wherein the changing the adjustable processor physical operating parameter based upon an error-tolerant performance criterion includes:

determining that changing the adjustable processor physical operating parameter is at least substantially likely to decrease a time to complete an execution of the sequence of instructions by the processor and changing the adjustable processor physical operating parameter based upon an error-tolerant performance criterion.

42. The method of claim 32, further comprising:

restoring an execution of the sequence of program instructions to a checkpoint based upon the detected processor-operating-parameter-caused error.

47. The method of claim 32, wherein the adjustable processor physical operating parameter includes:

an adjustable electrical operating parameter.

48. The method of claim 32, wherein the adjustable processor physical operating parameter includes:

an adjustable thermal operating parameter.

37. (canceled)

39. (canceled)

40. (canceled)

43. A device comprising:

means for detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable physical operating parameter; and

means for changing the adjustable processor physical operating parameter based upon an error-tolerant performance criterion.

44. The device of claim 43, further comprising:

means for restoring an execution of the sequence of program instructions to a checkpoint based upon the detected processor-operating-parameter-caused error.

49. A computing system comprising:

a processor system having an adjustable physical operating parameter;

an information store operable to save a sequence of instructions; and

a controller module including;

a monitor circuit for detecting an incidence of an error corresponding to an execution by the processor system of an instruction of the sequence of instructions; and

a control circuit for adjusting the adjustable physical operating parameter in response to the detected incidence of error and based upon an error-tolerant performance criterion.

50. A method implemented in a computerized system that includes a processor system having an adjustable physical operating parameter, the method comprising:

detecting an incidence of a processor error corresponding to an execution by the processor system of an instruction of a sequence of instructions; and

changing the adjustable processor physical operating parameter in response to the detected incidence of error and in response to an error-tolerant performance criterion.