Structure for a Circuit Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler

• US 20090132971A1
• Filed: 05/30/2008
• Published: 05/21/2009
• Est. Priority Date: 11/20/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Original Assignee: International Business Machines Corporation
• Inventors: Qi, Jieming, Hailu, Eskinder, Kaneko, Masaaki, Boerstler, David W.
• Granted Patent: US 8,108,813 B2
• Time in Patent Office: Days
• US Class Current: 716/132
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.

Claims

1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a plurality of first design structure elements representing a plurality of inverters;

a second design structure element representing a first control port coupled to the plurality of inverters, the first control port being configured to receive a frequency control voltage; and

a third design structure element representing a second control port coupled to the plurality of inverters, the second control port being configured to receive a duty cycle control voltage, wherein the design structure is configured such that a frequency of an output signal of the voltage controlled oscillator is controlled by the frequency control voltage received via the first control port and a duty cycle of the output signal is controlled by the duty cycle control voltage received via the second control port.

2. The design structure of claim 1, further comprising:

at least one fourth design structure element representing at least one duty cycle correction circuit coupled to the plurality of inverters and the second control port, wherein the design structure is configured such that the at least one duty cycle correction circuit adjusts a duty cycle of the output signal based on the duty cycle control voltage.

3. The design structure of claim 2, wherein the design structure is configured such that the at least one duty cycle correction circuit comprises a pair of transistors, and the pair of transistors adjust a pull up/down rate of at least one inverter in the plurality of inverters.

4. The design structure of claim 2, wherein the design structure is configured such that the plurality of inverters are provided in a loop configuration having a plurality of stages, the at least one duty cycle correction circuit comprises a plurality of duty cycle correction circuits, and the duty cycle correction circuits of the plurality of duty cycle correction circuits are coupled to every other stage of the loop.

5. The design structure of claim 2, wherein the design structure is configured such that the at least one duty cycle correction circuit increases a size of a low pulse of the output signal and reduces a size of a high pulse of the output signal in response to an increase in the duty cycle control voltage.

6. The design structure of claim 2, wherein the design structure is configured such that the at least one duty cycle correction circuit reduces a size of a low pulse of the output signal and increases a size of a high pulse of the output signal in response to a decrease in the duty cycle control voltage.

7. The design structure of claim 1, wherein the design structure is configured such that the frequency control voltage is received from a low pass filter of a phase/frequency locked loop and the duty cycle control voltage is received from an operational amplifier of a duty cycle loop.

8. The design structure of claim 7, wherein the design structure is configured such that the operational amplifier of the duty cycle loop generates the duty cycle control voltage based on a desired duty cycle control signal received from a controller.

9. The design structure of claim 8, wherein the design structure is configured such that the operation amplifier of the duty cycle loop further generates the duty cycle control voltage based on an output of the phase/frequency locked loop.

10. A design structure encoded on a machine-readable data storage medium, said design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a phase locked loop circuit, wherein said design structure comprises:

a plurality of first design structure elements representing a plurality of inverters;

a second design structure element representing a first control port coupled to the plurality of inverters, the first control port being configured to receive a frequency control voltage; and

a third design structure element representing a second control port coupled to the plurality of inverters, the second control port being configured to receive a duty cycle control voltage, wherein the design structure is configured such that a frequency of an output signal of the voltage controlled oscillator is controlled by the frequency control voltage received via the first control port and a duty cycle of the output signal is controlled by the duty cycle control voltage received via the second control port.

11. The design structure of claim 10, further comprising:

at least one fourth design structure element representing at least one duty cycle correction circuit coupled to the plurality of inverters and the second control port, wherein the design structure is configured such that the at least one duty cycle correction circuit adjusts a duty cycle of the output signal based on the duty cycle control voltage.

12. The design structure of claim 11, wherein the design structure is configured such that the at least one duty cycle correction circuit comprises a pair of transistors, and the pair of transistors adjust a pull up/down rate of at least one inverter in the plurality of inverters.

13. The design structure of claim 11, wherein the design structure is configured such that the plurality of inverters are provided in a loop configuration having a plurality of stages, the at least one duty cycle correction circuit comprises a plurality of duty cycle correction circuits, and the duty cycle correction circuits of the plurality of duty cycle correction circuits are coupled to every other stage of the loop.

14. The design structure of claim 11, wherein the design structure is configured such that the at least one duty cycle correction circuit increases a size of a low pulse of the output signal and reduces a size of a high pulse of the output signal in response to an increase in the duty cycle control voltage.

15. The design structure of claim 11, wherein the design structure is configured such that the at least one duty cycle correction circuit reduces a size of a low pulse of the output signal and increases a size of a high pulse of the output signal in response to a decrease in the duty cycle control voltage.

16. The design structure of claim 10, wherein the design structure is configured such that the frequency control voltage is received from a low pass filter of a phase/frequency locked loop and the duty cycle control voltage is received from an operational amplifier of a duty cycle loop.

17. The design structure of claim 16, wherein the design structure is configured such that the operational amplifier of the duty cycle loop generates the duty cycle control voltage based on a desired duty cycle control signal received from a controller.

18. The design structure of claim 17, wherein the design structure is configured such that the operation amplifier of the duty cycle loop further generates the duty cycle control voltage based on an output of the phase/frequency locked loop.

19. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a phase locked loop circuit, wherein said HDL design structure comprises:

a plurality of first design structure elements representing a plurality of inverters;

a second design structure element representing a first control port coupled to the plurality of inverters, the first control port being configured to receive a frequency control voltage; and

a third design structure element representing a second control port coupled to the plurality of inverters, the second control port being configured to receive a duty cycle control voltage, wherein the design structure is configured such that a frequency of an output signal of the voltage controlled oscillator is controlled by the frequency control voltage received via the first control port and a duty cycle of the output signal is controlled by the duty cycle control voltage received via the second control port.

20. The design structure of claim 19, further comprising:

at least one fourth design structure element representing at least one duty cycle correction circuit coupled to the plurality of inverters and the second control port, wherein the design structure is configured such that the at least one duty cycle correction circuit adjusts a duty cycle of the output signal based on the duty cycle control voltage.

21. The design structure of claim 20, wherein the design structure is configured such that the at least one duty cycle correction circuit comprises a pair of transistors, and the pair of transistors adjust a pull up/down rate of at least one inverter in the plurality of inverters.

22. The design structure of claim 20, wherein the design structure is configured such that the plurality of inverters are provided in a loop configuration having a plurality of stages, the at least one duty cycle correction circuit comprises a plurality of duty cycle correction circuits, and the duty cycle correction circuits of the plurality of duty cycle correction circuits are coupled to every other stage of the loop.

23. The design structure of claim 20, wherein the design structure is configured such that the at least one duty cycle correction circuit increases a size of a low pulse of the output signal and reduces a size of a high pulse of the output signal in response to an increase in the duty cycle control voltage.

24. The design structure of claim 20, wherein the design structure is configured such that the at least one duty cycle correction circuit reduces a size of a low pulse of the output signal and increases a size of a high pulse of the output signal in response to a decrease in the duty cycle control voltage.

25. The design structure of claim 19, wherein the design structure is configured such that the frequency control voltage is received from a low pass filter of a phase/frequency locked loop and the duty cycle control voltage is received from an operational amplifier of a duty cycle loop.

26. A method in a computer-aided design system for generating a functional design model of a duty cycle correction circuit, said method comprising:

generating a functional computer-simulated representation of a plurality of inverters;

generating a functional computer-simulated representation of a first control port coupled to the plurality of inverters, the first control port being configured to receive a frequency control voltage; and

generating a functional computer-simulated representation of a second control port coupled to the plurality of inverters, the second control port being configured to receive a duty cycle control voltage, wherein the functional design model is configured such that a frequency of an output signal of the voltage controlled oscillator is controlled by the frequency control voltage received via the first control port and a duty cycle of the output signal is controlled by the duty cycle control voltage received via the second control port.