Structure for a Circuit Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler
First Claim
1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
- a plurality of first design structure elements representing a plurality of inverters;
a second design structure element representing a first control port coupled to the plurality of inverters, the first control port being configured to receive a frequency control voltage; and
a third design structure element representing a second control port coupled to the plurality of inverters, the second control port being configured to receive a duty cycle control voltage, wherein the design structure is configured such that a frequency of an output signal of the voltage controlled oscillator is controlled by the frequency control voltage received via the first control port and a duty cycle of the output signal is controlled by the duty cycle control voltage received via the second control port.
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Accused Products
Abstract
A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.
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Citations
26 Claims
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1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
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a plurality of first design structure elements representing a plurality of inverters; a second design structure element representing a first control port coupled to the plurality of inverters, the first control port being configured to receive a frequency control voltage; and a third design structure element representing a second control port coupled to the plurality of inverters, the second control port being configured to receive a duty cycle control voltage, wherein the design structure is configured such that a frequency of an output signal of the voltage controlled oscillator is controlled by the frequency control voltage received via the first control port and a duty cycle of the output signal is controlled by the duty cycle control voltage received via the second control port. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A design structure encoded on a machine-readable data storage medium, said design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a phase locked loop circuit, wherein said design structure comprises:
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a plurality of first design structure elements representing a plurality of inverters; a second design structure element representing a first control port coupled to the plurality of inverters, the first control port being configured to receive a frequency control voltage; and a third design structure element representing a second control port coupled to the plurality of inverters, the second control port being configured to receive a duty cycle control voltage, wherein the design structure is configured such that a frequency of an output signal of the voltage controlled oscillator is controlled by the frequency control voltage received via the first control port and a duty cycle of the output signal is controlled by the duty cycle control voltage received via the second control port. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a phase locked loop circuit, wherein said HDL design structure comprises:
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a plurality of first design structure elements representing a plurality of inverters; a second design structure element representing a first control port coupled to the plurality of inverters, the first control port being configured to receive a frequency control voltage; and a third design structure element representing a second control port coupled to the plurality of inverters, the second control port being configured to receive a duty cycle control voltage, wherein the design structure is configured such that a frequency of an output signal of the voltage controlled oscillator is controlled by the frequency control voltage received via the first control port and a duty cycle of the output signal is controlled by the duty cycle control voltage received via the second control port. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A method in a computer-aided design system for generating a functional design model of a duty cycle correction circuit, said method comprising:
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generating a functional computer-simulated representation of a plurality of inverters; generating a functional computer-simulated representation of a first control port coupled to the plurality of inverters, the first control port being configured to receive a frequency control voltage; and generating a functional computer-simulated representation of a second control port coupled to the plurality of inverters, the second control port being configured to receive a duty cycle control voltage, wherein the functional design model is configured such that a frequency of an output signal of the voltage controlled oscillator is controlled by the frequency control voltage received via the first control port and a duty cycle of the output signal is controlled by the duty cycle control voltage received via the second control port.
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Specification