Driving Values to DC Adjusted/Untimed Nets to Identify Timing Problems

• US 20090132983A1
• Filed: 11/14/2008
• Published: 05/21/2009
• Est. Priority Date: 07/17/2006
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ja, Yee, Gass, Robert B., Jaeschke, Christoph
• Granted Patent: US 7,886,244 B2
• Time in Patent Office: Days
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

An apparatus and computer program product for driving values to “don'"'"'t care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.

Claims

1-10. -10. (canceled)

11. A computer program product comprising a computer useable medium having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:

receive an integrated circuit design;

receive a “

don'"'"'t care”

(DC) adjusted list that identifies net segments that do not need to adhere to timing requirements;

compare entries in the DC adjusted list to a netlist for the integrated circuit design to identify an untimed net segment based on a match of a net segment in the DC adjusted list with a net in the netlist for the integrated circuit design;

drive a value along a pathway to the at least one untimed net segment;

monitor an output state value from the untimed net segment;

verify an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment;

determine whether there is a violation in the operation of the untimed net segment;

determine whether downstream logic in the integrated circuit design uses the output value; and

remove the untimed net segment from the DC adjusted list if there is a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design does not use the output value.

12. The computer program product of claim 11, wherein the operation of the untimed net segment is verified if the output value from the untimed net segment maintains a predetermined value.

13. The computer program product of claim 11, wherein the operation of the untimed net segment is not verified if the output value from the untimed net segment achieves a value different from a predetermined value.

14. The computer program product of claim 11, wherein the computer readable program further causes the computing device to replicate, in the integrated circuit design, a pathway to the untimed net segment, and wherein the computer readable program causes the computing device to drive the value along a pathway to the at least one untimed net segment by driving the value along the replicated pathway to the untimed net segment.

16. The computer program product of claim 11, wherein the computer readable program causes the computing device to drive a value along a pathway to the at least one untimed net segment by:

driving one of an indeterminate value or a random value along the pathway to the at least one untimed net segment; and

performing one of formal, semi-formal, or non-formal verification analysis on the integrated circuit design using the driven value.

17. The computer program product of claim 16, wherein the verification analysis uses a logical built-in self test mode of operation of the integrated circuit device.

18. The computer program product of claim 13, wherein the computer readable program further causes the computing device to:

output a result of the verification, wherein the result identifies untimed net segments that are not verified as maintaining the predetermined value.

19. The computer program product of claim 11, wherein an indeterminate value is driven along the pathway to the at least one untimed net segment, and wherein if the collected output value from the untimed net is an indeterminate value, the untimed net segment is determined to be invalid.

15. (canceled)

20. An apparatus, comprising:

a processor; and

a memory coupled to the processor, wherein the memory contains instructions which, when executed by the processor, cause the processor to;

receive an integrated circuit design;

receive a “

don'"'"'t care”

(DC) adjusted list that identifies net segments that do not need to adhere to timing requirements;

compare entries in the DC adjusted list to a netlist for the integrated circuit design to identify an untimed net segment based on a match of a net segment in the DC adjusted list with a net in the netlist for the integrated circuit design;

drive a value along a pathway to the at least one untimed net segment;

monitor an output state value from the untimed net segment;

verify an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment;

determine whether there is a violation in the operation of the untimed net segment;

determine whether downstream logic in the integrated circuit design uses the output value; and

remove the untimed net segment from the DC adjusted list if there is a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design does not use the output value.

21. The apparatus of claim 20, wherein the operation of the untimed net segment is verified if the output value from the untimed net segment maintains a predetermined value.

22. The apparatus of claim 20, wherein the operation of the untimed net segment is not verified if the output value from the untimed net segment achieves a value different from a predetermined value.

23. The apparatus of claim 20, wherein the instructions further cause the processor to replicate, in the integrated circuit design, a pathway to the untimed net segment, and wherein the computer readable program causes the computing device to drive the value along a pathway to the at least one untimed net segment by driving the value along the replicated pathway to the untimed net segment.

24. The apparatus of claim 20, wherein the instructions further cause the processor to drive a value along a pathway to the at least one untimed net segment by:

driving one of an indeterminate value or a random value along the pathway to the at least one untimed net segment; and

performing one of formal, semi-formal, or non-formal verification analysis on the integrated circuit design using the driven value.

25. The apparatus of claim 20, wherein an indeterminate value is driven along the pathway to the at least one untimed net segment, and wherein if the collected output value from the untimed net is an indeterminate value, the untimed net segment is determined to be invalid.

26. The apparatus of claim 20, wherein the instructions further cause the processor to:

responsive to there being a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design using the output value, notifying a designer that the untimed net segment has a timing error.

27. A computer program product comprising a computer useable medium having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:

receive the integrated circuit design;

receive a “

don'"'"'t care”

(DC) adjusted list that identifies net segments that do not need to adhere to timing requirements;

compare entries in the DC adjusted list to a netlist for the integrated circuit design to identify an untimed net segment based on a match of a net segment in the DC adjusted list with a net in the netlist for the integrated circuit design;

convert the untimed net segment to single source and single sink net;

identify a source latch that feeds the untimed net segment;

identify, in the integrated circuit design, a path to the untimed net segment from its source latch;

replicate, in the integrated circuit design, the identified path to form a replicated path;

drive a value to the untimed net segment along the identified path and the replicated path;

monitor an output state value from the untimed net segment; and

verify an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment;

determine whether there is a violation in the operation of the untimed net segment;

determine whether downstream logic in the integrated circuit design uses the output value; and

remove the untimed net segment from the DC adjusted list if there is a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design does not use the output value.

28. The computer program product of claim 27, wherein the operation of the untimed net segment is verified if the output value from the untimed net segment maintains a predetermined value.

29. The computer program product of claim 27, wherein driving a value to the at least one untimed net segment comprises:

driving one of an indeterminate value or a random value to the at least one untimed net segment; and

performing one of formal, semi-formal, or non-formal verification analysis on the integrated circuit design using the driven value.

30. The computer program product of claim 27, wherein an indeterminate value is driven to the at least one untimed net segment, and wherein if the collected output value from the untimed net is an indeterminate value, the untimed net segment is determined to be invalid.

31. The computer program product of claim 27, wherein converting the untimed net segment to single source and single sink net comprises inserting at least one transparent latch into the integrated circuit design.