PASSIVE CIRCUIT FOR IMPROVED DIFFERENTIAL AMPLIFIER COMMON MODE REJECTION

• US 20090133083A1
• Filed: 11/21/2007
• Published: 05/21/2009
• Est. Priority Date: 11/21/2007
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ezra, Ronen, Ben-Hamo, Oren, Klein, Shaul, Meir, Moshe
• Application Number:
  US11/943,665
• Publication Number:
  US 20090133083A1
• Time in Patent Office: Days
• US Class Current: 725/111
• CPC Class Codes: H03F 2200/09 A balun, i.e. balanced to or from unbalanced converter, being present at the output of an amplifier
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 2203/45731 the LC comprising a transformer
• CPC Class Codes: H03F 3/45085 Long tailed pairs H03F3/45112, H03F3/45139 take precedence
• CPC Class Codes: H03F 3/45618 by using balancing means

Abstract

A novel passive circuit for providing improved common mode rejection of a differential amplifier novel. The passive circuit functions to compensate for amplitude mismatches between the two outputs of a differential amplifier. To compensate for the amplitude mismatch between the output traces of the amplifier, a resistor is inserted in series with at either one or both of the differential outputs. The values of the resistors are set such that the mismatch is substantially eliminated. Inductors are connected in parallel with the resistors to create a zero ohm path for power. At high frequencies the inductor impedance is sufficiently high that the series resistor compensates for the imbalance caused by spurious products. The imbalance in the amplifier outputs is corrected with the resulting increase in the rejection of spurious frequency products by exploiting the differential common mode rejection (CMR) effect of the differential amplifier.

Claims

1. A circuit, comprising:

a differential amplifier operative to generate a differential output comprising a first output and a second output;

a parallel R-L circuit connected in series with said first output; and

wherein said R-L circuit is operative to substantially compensate for any amplifier mismatch between said first output and said second output.

2. The circuit according to claim 1, wherein said differential amplifier comprises a programmable gain amplifier.

3. The circuit according to claim 1, further comprising a center tapped transformer coupled to said first output and said second output, wherein said center tap is coupled to a power supply and operative to provide power to said differential amplifier via said first output and said second output.

4. The circuit according to claim 1, further comprising a balun coupled to said first output and said second output, wherein the common mode noise rejection of said balun is significantly improved by the operation of said parallel R-L circuit.

5. The circuit according to claim 1, wherein the value of a resistor portion of said parallel R-L circuit is selected so as to compensate for attenuation mismatch between said differential amplifier first and second outputs.

6. The circuit according to claim 1, wherein said parallel R-L circuit comprises a resistor and inductor, wherein said inductor provides a substantially zero impedance path for a power supply input to said differential amplifier.

7. A circuit, comprising:

a differential amplifier operative to generate a differential output comprising a first output and a second output;

a first parallel R-L circuit connected in series with said first output;

a second parallel R-L circuit connected in series with said second output; and

wherein said first R-L circuit and said second R-L circuit are operative to substantially compensate for any amplifier mismatch between said first output and said second output.

8. The circuit according to claim 7, wherein said differential amplifier comprises a programmable gain amplifier.

9. The circuit according to claim 7, further comprising a center tapped transformer coupled to said first output and said second output, wherein said center tap is coupled to a power supply and operative to provide power to said differential amplifier via said first output and said second output.

10. The circuit according to claim 7, further comprising a balun coupled to said first output and said second output, wherein the common mode noise rejection of said balun is significantly improved by the operation of said parallel R-L circuit.

11. The circuit according to claim 7, wherein the values of the resistor portions of said first and second parallel R-L circuits are selected so as to compensate for attenuation mismatch between said differential amplifier first and second outputs.

12. The circuit according to claim 7, wherein said first parallel R-L circuit comprises a first resistor and a first inductor, said second parallel R-L circuit comprises a second resistor and a second inductor, said first inductor and second inductor providing a substantially zero impedance path for a DC power supply input to said differential amplifier.

13. A circuit, comprising:

first means for compensating for amplifier mismatch between first and second outputs of a differential amplifier; and

second means for providing a substantially zero impedance path for a DC power supply coupled to said first and second outputs.

14. The circuit according to claim 13, wherein said first means comprises a resistor connected in series with one of said first output or said second output.

15. The circuit according to claim 13, wherein said first means comprises:

a first resistor connected in series with said first output;

a second resistor connected in series with said second output; and

wherein the values of said first and second resistors are selected so as to substantially compensate for any amplifier mismatch between said first output and said second output.

16. The circuit according to claim 13, wherein said second means comprises an inductor connected in parallel with said resistor.

17. The circuit according to claim 13, wherein said second means comprises:

a first inductor connected in parallel with said first resistor; and

a second inductor connected in parallel with said second resistor.

18. The circuit according to claim 17, wherein the values of said first and second inductors are equal.

19. A circuit, comprising:

a differential amplifier operative to generate a differential output comprising a first output and a second output;

conversion means having a differential input and a single ended output, said conversion means operative to convert the differential output of said differential amplifier to a single ended signal and to provide DC power to said differential amplifier via a center tap connected to a DC power supply voltage;

a first parallel R-L circuit connected in series with said first output and one end of the differential input of said conversion means;

a second parallel R-L circuit connected in series with said second output and a second end of the differential input of said conversion means; and

wherein said first R-L circuit and said second R-L circuit operative to substantially compensate for amplifier mismatch between said first output and said second output while providing a substantially zero impedance path for said DC power supply voltage.

20. The circuit according to claim 19, wherein said circuit is implemented in an upstream path in a Data Over Cable Service Interface Specification (DOCSIS) compatible cable modem.

21. The circuit according to claim 19, wherein said conversion means comprises a signal transformer.

22. The circuit according to claim 19, wherein said conversion means comprises a balun.

23. A cable modem, comprising:

a memory;

one or more interface ports;

a downstream system connected to a CATV radio frequency (RF) signal input and operative to output a plurality of channel data therefrom;

an upstream system connected to said CATV radio frequency (RF) signal input, said upstream system comprising;

a differential amplifier operative to generate a differential output comprising a first output and a second output;

a balun having a differential input and a single ended output, said balun operative to convert the differential output of said differential amplifier to a single ended signal and to provide DC power to said differential amplifier via a center tap connected to a DC power supply voltage;

a first parallel R-L circuit connected in series with said first output and one end of the differential input of said balun;

a second parallel R-L circuit connected in series with said second output and a second end of the differential input of said balun;

wherein said first R-L circuit and said second R-L circuit operative to substantially compensate for amplifier mismatch between said first output and said second output while providing a substantially zero impedance path for said DC power supply voltage; and

a processor coupled to said memory, said one or more interface ports, said downstream system and said upstream system, said processor operative to implement a media access control (MAC) layer operative to generate a plurality of output channels.

24. The cable modem according to claim 23, wherein said plurality of output channels comprises Data Over Cable Service Interface Specification (DOCSIS) channels.

25. The cable modem according to claim 23, wherein the values of the resistor portions of said first and second parallel R-L circuits are selected so as to compensate for attenuation mismatch between said first and second outputs of said differential output.