Through Substrate Via Semiconductor Components
First Claim
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1. A method for forming a first semiconductor component, the method comprising:
- forming landing pads on a top side of a substrate, the landing pads comprising multiple levels of conductive plates connected by conductive vias;
forming trenches in the substrate, wherein an etch for forming trenches starts from a lower surface of the substrate and etches through the substrate and all material layers between the substrate and the landing pads; and
forming through-vias in the substrate by lining the trenches with an insulator and filling the lined trenches with a conducting material.
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Abstract
A structure and method of forming landing pads for through substrate vias in forming stacked semiconductor components are described. In various embodiments, the current invention describes landing pad structures that includes multiple levels of conductive plates connected by vias such that the electrical connection between a through substrate etch and landing pad is independent of the location of the bottom of the through substrate trench.
118 Citations
25 Claims
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1. A method for forming a first semiconductor component, the method comprising:
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forming landing pads on a top side of a substrate, the landing pads comprising multiple levels of conductive plates connected by conductive vias; forming trenches in the substrate, wherein an etch for forming trenches starts from a lower surface of the substrate and etches through the substrate and all material layers between the substrate and the landing pads; and forming through-vias in the substrate by lining the trenches with an insulator and filling the lined trenches with a conducting material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for forming a through substrate via, the method comprising:
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forming a landing pad over a top surface of a substrate, the landing pad separated from the substrate by an insulating material layer, wherein the landing pad comprises multiple levels of conductive plates connected by conductive vias; aligning a lithographic mask on a bottom surface of the substrate, wherein the lithographic mask is aligned with respect to at least one landing pad; forming a pattern on the bottom surface using the aligned lithographic mask; forming a trench in the substrate, wherein an etch for forming the trench starts from the bottom surface and etches through the substrate and stops inside the insulating material layer; depositing a dielectric layer on exposed surfaces of the trench; etching the trench further into the insulating material layer and stopping on the landing pad; conformally lining the trench with a conducting diffusion barrier material; and filling the lined trench with a conducting material. - View Dependent Claims (10)
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11. A through substrate via semiconductor device comprising:
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a substrate comprising an upper surface and an opposite lower surface, wherein active devices are disposed in the upper surface; a landing pad disposed above the upper surface of the substrate, wherein the landing pad comprises multiple levels of conductive plates connected by conductive vias; and a through-via with a bottom surface disposed in the substrate and extending from the lower surface through the upper surface of the substrate and into the landing pad. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A through substrate via semiconductor device comprising:
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a semiconductor chip comprising a substrate, the substrate comprising an upper surface and an opposite lower surface, wherein active devices are disposed in the upper surface; landing pads disposed on a top side of the semiconductor chip, wherein the landing pads comprise; multiple levels of conductive plates disposed above the upper surface; and at least one via level connecting the multiple levels of conductive plates; and at least one through-via with a bottom surface, the at least one through-via extending from the lower surface through the upper surface into the landing pads, wherein the at least one through-via establishes an electrical connection with the landing pads independent of a location of a bottom surface in the landing pads, and wherein the at least one through-via is lined with a dielectric layer that extends from the lower surface to the upper surface but not into an etched portion of the landing pads. - View Dependent Claims (22, 23)
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24. A semiconductor component comprising:
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a first region comprising a first landing pad structure disposed above a substrate; a first through substrate via disposed inside the substrate, the first through substrate via contacting the first landing pad structure at a first distance above the substrate; a second region comprising a second landing pad structure disposed above the substrate; and a second through substrate via disposed inside the substrate, the second through substrate via contacting the second landing pad structure at a second distance above the substrate, wherein the ratio of the first distance to the second distance is greater than about 1.1. - View Dependent Claims (25)
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Specification