Method of manufacturing semiconductor device and semiconductor device

• US 20090134516A1
• Filed: 12/04/2008
• Published: 05/28/2009
• Est. Priority Date: 02/23/2005
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Seto, Masaharu, Ezawa, Hirokazu
• Application Number:
  US12/314,135
• Publication Number:
  US 20090134516A1
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/1146 Plating
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11502 Pre-existing or pre-deposited material
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/119 Methods of manufacturing bump connectors involving a specific sequence of method steps
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/11906 with modification of the same mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

Claims

1-12. -12. (canceled)

13. A semiconductor device, comprising:

a substrate;

a conducting layer which is formed on the substrate;

a first plated film which is formed on the conducting layer; and

a second plated film which is formed on the conducting layer to cover the top and side surfaces of the first plated film.

14. The semiconductor device according to claim 13, wherein the substrate comprises an electrode pad, and the conducting layer is in contact with the electrode pad.

15. The semiconductor device according to claim 13, wherein the first plated film serves as relocation wiring.

16. The semiconductor device according to claim 15, wherein the second plated film has an opening and further comprising a solder bump which is electrically connected to the first plated film via the opening.

17. The semiconductor device according to claim 13, wherein the first plated film is formed of any of Cu, Ag and Au.

18. The semiconductor device according to claim 13, wherein the second plated film is formed of either Sn or polyimide.

19. The semiconductor device according to claim 13, wherein the first plated film is formed of Ag, and second plated film is formed of Sn.

20. The semiconductor device according to claim 13, wherein the conducting layer has a function to suppress a material forming the first plated film or the second plated film from diffusing.