Method of optimum current blanking time implementation in current sense circuit

• US 20090134856A1
• Filed: 11/26/2007
• Published: 05/28/2009
• Est. Priority Date: 11/26/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Li, Zheng, Smith, Brett E., Li, Huijuan, Rahman, Abidur
• Granted Patent: US 7,868,599 B2
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

In a method and system for sensing current in a switching regulator (SWR) operating in a current mode, a power switch is coupled to receive the current from a switching element, the power switch being controlled by a gate signal. An inrush of the current causes an initial transient spike (ITS). A buffer having a buffer input and a buffer output is coupled to receive the gate signal and provide a buffered gate signal. The buffer output is disabled during the ITS. A sense switch (SW) is coupled to receive a portion of the current from the switching element, the SW being turned on by the buffered gate signal after the initial transient spike. A sense resistor (SR) is coupled to receive the portion of the current from the SW. An amplifier converts the portion of the current through the SR to a voltage signal for controlling the SWR.

Claims

1. A current sensing circuit comprising:

a power switch coupled to receive a current from a switching input, the power switch being controlled by a gate signal, wherein a turn on of the power switch causes the current to have an initial transient spike;

a buffer having a buffer input and a buffer output, the buffer input being coupled to receive the gate signal and provide a buffered gate signal at the buffer output, wherein the buffer output is disabled during the initial transient spike;

a sense switch coupled to receive a portion of the current from the switching input, the sense switch being turned on by the buffered gate signal after the initial transient spike; and

a sense resistor coupled to receive the portion of the current from the sense switch.

2. The current sensing circuit of claim 1, wherein the buffer includes:

a first inverter having a first inverter input and a first inverter output, wherein the first inverter input is coupled to the buffer input, wherein the first inverter is configured to disable the first inverter output when the gate signal is less than an input high threshold (Vih) voltage, the Vih being configured to be greater than a worst case Miller plateau voltage of the power switch; and

a second inverter having a second inverter input and a second inverter output, wherein the second inverter input is coupled to the first inverter output and the second inverter output is coupled to the buffer output, wherein the buffer output is disabled when the gate signal is less than the Vih.

3. The current sensing circuit of claim 1, wherein a ratio of the portion of the current flowing through the sense switch and the current flowing through the power switch is proportional to an on-resistance of the power switch and a combined resistance of the sense resistor and an on-resistance of the sense switch.

4. The current sensing circuit of claim 1 further comprising:

an amplifier having a pair of inputs and a voltage output, wherein the pair of inputs are coupled across the sense resistor, wherein a voltage provided at the voltage output is proportional to the current.

5. The current sensing circuit of claim 1, wherein a time difference between the power switch being turned on and the sense switch being turned on is a current blanking time, wherein the initial transient spike subsides during the current blanking time.

6. The current sensing circuit of claim 1, wherein the current blanking time is reduced compared to a current blanking time for a traditional current blanking circuit.

7. The current sensing circuit of claim 1, wherein a silicon area to implement the current sensing circuit is reduced compared to a silicon area to implement the traditional current sensing circuit.

8. The current sensing circuit of claim 1, wherein the current sensing circuit is included in a switching regulator operating in a current mode, wherein the switching regulator is a DC-DC converter.

9. The current sensing circuit of claim 8, wherein the DC-DC converter is one of a boost converter, a buck converter, a buck-boost converter, and a Cuk converter or a combination thereof.

10. A method of sensing a current flowing through a power switch of a switching regulator, the method comprising:

turning on the power switch to enable the current to flow, the turning on causing an initial transient spike in the current;

controlling a sense switch to turn on after the occurrence of the initial transient spike, the sense switch being operable to sense a portion of the current.

11. In the method of claim 10, wherein the controlling includes:

disposing a buffer between a gate of the power switch and a gate of the sense switch; and

configuring the buffer to have an input high threshold (Vih) voltage greater than a worst case Miller plateau voltage of the power switch, thereby disabling the buffer to turn on the sense switch during the occurrence of the initial transient spike.

12. In the method of claim 10 further comprising:

measuring a voltage across a sense resistor coupled in series with a source of the sense switch, wherein the voltage is a value of the sense resistor multiplied by the portion of the current flowing through the sense switch.

13. In the method of claim 10, wherein a combination of the sense switch and the sense resistor is coupled in parallel with the power switch.

14. In the method of claim 10, wherein a time difference between the power switch being turned on and the sense switch being turned on is a current blanking time, wherein the initial transient spike subsides during the current blanking time.

15. In the method of claim 10, wherein the switching regulator is a DC-DC converter.

16. In the method of claim 15, wherein the DC-DC converter is one of a boost converter, a buck converter, a buck-boost converter, and a Cuk converter or a combination thereof.

17. An electronic system comprising:

a load; and

a switching regulator operable to provide power to the load, the switching regulator including;

an energy storage element coupled to receive a voltage input at an input terminal;

a current sensing circuit including;

a power switch coupled to receive a current from the energy storage element, the power switch being controlled by a gate signal, wherein an inrush of the current causes an initial transient spike;

a buffer having a buffer input and a buffer output, the buffer input being coupled to receive the gate signal and provide a buffered gate signal at the buffer output, wherein the buffer output is disabled during the initial transient spike;

a sense switch coupled to receive a portion of the current from the energy storage element, the sense switch being turned on by the buffered gate signal after the initial transient spike;

a sense resistor coupled to receive the portion of the current from the sense switch;

an amplifier operable to convert the portion of the current through the sense resistor to a feedback signal;

a controller coupled to receive the feedback signal derived as a function of the current flowing through the energy storage element, wherein the controller provides the gate signal in response to the feedback signal.

18. The system of claim 17, wherein the load is at least one of a microprocessor, an application specific integrated circuit (ASIC), a digital signal processor, a radio frequency chip, a memory, a microcontroller, and a system-on-a-chip, or a combination thereof.

19. The system of claim 17, wherein the switching regulator is a DC-DC converter, wherein the DC-DC converter is one of a boost converter, a buck converter, a buck-boost converter, and a Cuk converter or a combination thereof.

20. The system of claim 17, wherein a time difference between the power switch being turned on and the sense switch being turned on is a current blanking time, wherein the current blanking time is reduced compared to a current blanking time for a traditional current blanking circuit.