ZERO-DELAY BUFFER WITH COMMON-MODE EQUALIZER FOR INPUT AND FEEDBACK DIFFERENTIAL CLOCKS INTO A PHASE-LOCKED LOOP (PLL)
First Claim
1. A differential clock generator comprising:
- a reference clock input for receiving a reference clock, wherein the reference clock is a differential clock represented by a difference of signals carried by a true signal line and by a complement signal line;
a first differential clock buffer, receiving the reference clock on a true input and on a complement input, the first differential clock buffer sensing a voltage difference between the true input and the complement input and driving a true output and a complement output with a buffered reference clock;
a first differential-to-single-ended (DTS) converter, receiving the buffered reference clock on a true input and on a complement input, the first DTS converter generating a combined reference clock signal as a difference of the true input and the complement input;
a second differential clock buffer, receiving a feedback clock on a true input and on a complement input, the second differential clock buffer sensing a voltage difference between the true input and the complement input and driving a true output and a complement output with a buffered feedback clock;
a second DTS converter, receiving the buffered feedback clock on a true input and on a complement input, the second DTS converter generating a combined feedback clock signal as a difference of the true input and the complement input;
a phase detector having a first input that receives the combined reference clock signal from the first DTS converter and having a second input that receives the combined feedback clock signal from the second DTS converter, the phase detector detecting a phase difference between the combined reference clock signal and the combined feedback clock signal and generating an up signal and a down signal in response to the phase difference detected;
a sensing capacitor for storing charge to generate a sensing voltage;
a first charge pump, activated by the up signal from the phase detector, for charging the sensing capacitor;
a second charge pump, activated by the down signal from the phase detector, for discharging the sensing capacitor;
a voltage-controlled oscillator (VCO) that receives the sensing voltage from the sensing capacitor, the VCO generating the feedback clock with a frequency that is dependent on the sensing voltage, wherein the VCO outputs a true signal and a complement signal for the feedback clock;
an output differential clock buffer, receiving the feedback clock on a true input and on a complement input, the output differential clock buffer sensing a voltage difference between the true input and the complement input and driving a true output and a complement output with a buffered output clock;
a first common-mode sensor, coupled to the first differential clock buffer to sense a first common-mode voltage of the true output and the complement output from the first differential clock buffer;
a second common-mode sensor, coupled to the second differential clock buffer to sense a second common-mode voltage of the true output and the complement output from the second differential clock buffer; and
a second equalizer, receiving the second common-mode voltage from the second common-mode sensor, and receiving the second common-mode voltage from the second common-mode sensor, for generating a second control voltage;
wherein the second control voltage is applied to the second differential clock buffer, the second control voltage adjusting the second common-mode voltage of the true output and the complement output from the second differential clock buffer,whereby the second common-mode voltage is adjusted by the second equalizer and the second common-mode sensor.
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Accused Products
Abstract
A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.
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Citations
20 Claims
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1. A differential clock generator comprising:
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a reference clock input for receiving a reference clock, wherein the reference clock is a differential clock represented by a difference of signals carried by a true signal line and by a complement signal line; a first differential clock buffer, receiving the reference clock on a true input and on a complement input, the first differential clock buffer sensing a voltage difference between the true input and the complement input and driving a true output and a complement output with a buffered reference clock; a first differential-to-single-ended (DTS) converter, receiving the buffered reference clock on a true input and on a complement input, the first DTS converter generating a combined reference clock signal as a difference of the true input and the complement input; a second differential clock buffer, receiving a feedback clock on a true input and on a complement input, the second differential clock buffer sensing a voltage difference between the true input and the complement input and driving a true output and a complement output with a buffered feedback clock; a second DTS converter, receiving the buffered feedback clock on a true input and on a complement input, the second DTS converter generating a combined feedback clock signal as a difference of the true input and the complement input; a phase detector having a first input that receives the combined reference clock signal from the first DTS converter and having a second input that receives the combined feedback clock signal from the second DTS converter, the phase detector detecting a phase difference between the combined reference clock signal and the combined feedback clock signal and generating an up signal and a down signal in response to the phase difference detected; a sensing capacitor for storing charge to generate a sensing voltage; a first charge pump, activated by the up signal from the phase detector, for charging the sensing capacitor; a second charge pump, activated by the down signal from the phase detector, for discharging the sensing capacitor; a voltage-controlled oscillator (VCO) that receives the sensing voltage from the sensing capacitor, the VCO generating the feedback clock with a frequency that is dependent on the sensing voltage, wherein the VCO outputs a true signal and a complement signal for the feedback clock; an output differential clock buffer, receiving the feedback clock on a true input and on a complement input, the output differential clock buffer sensing a voltage difference between the true input and the complement input and driving a true output and a complement output with a buffered output clock; a first common-mode sensor, coupled to the first differential clock buffer to sense a first common-mode voltage of the true output and the complement output from the first differential clock buffer; a second common-mode sensor, coupled to the second differential clock buffer to sense a second common-mode voltage of the true output and the complement output from the second differential clock buffer; and a second equalizer, receiving the second common-mode voltage from the second common-mode sensor, and receiving the second common-mode voltage from the second common-mode sensor, for generating a second control voltage; wherein the second control voltage is applied to the second differential clock buffer, the second control voltage adjusting the second common-mode voltage of the true output and the complement output from the second differential clock buffer, whereby the second common-mode voltage is adjusted by the second equalizer and the second common-mode sensor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A differential phase-locked loop (PLL) comprising:
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a differential reference clock characterized by a first input common-mode voltage of a first pair of differential signals carrying the differential reference clock; a differential feedback clock characterized by a second input common-mode voltage of a second pair of differential signals carrying the differential feedback clock; wherein the first input common-mode voltage and the second input common-mode voltage are different voltages; a first differential buffer receiving the first pair carrying the differential reference clock, and generating a first buffered pair carrying a differential buffered reference clock; a first differential-to-single-ended converter, receiving the first buffered pair, and generating a first single-ended clock; a second differential buffer receiving the second pair carrying the differential feedback clock, and generating a second buffered pair carrying a differential buffered feedback clock; a second differential-to-single-ended converter, receiving the second buffered pair, and generating a second single-ended clock; a first common-mode sensor, coupled to the first differential buffer, for generating a first sensed common-mode voltage; a second common-mode sensor, coupled to the second differential buffer, for generating a second sensed common-mode voltage; a first equalizer, receiving the first sensed common-mode voltage, for adjusting a common-mode voltage of the first buffered pair carrying the differential buffered reference clock in response to the first sensed common-mode voltage; a phase comparator, receiving the first single-ended clock from the first differential-to-single-ended converter, and receiving the second single-ended clock from the second differential-to-single-ended converter, for generating a charge signal and a discharge signal in response to a phase difference between the first single-ended clock and the second single-ended clock; a filter capacitor generating a sense voltage; a charger for charging the filter capacitor in response to the charge signal from the phase comparator; a discharger for discharging the filter capacitor in response to the discharge signal from the phase comparator; and a voltage-controlled oscillator that generates the differential feedback clock having a frequency controlled by the sense voltage of the filter capacitor, whereby static phase offset between the differential reference clock and the differential feedback clock caused by a difference in the first input common-mode voltage and the second input common-mode voltage is compensated for by the first equalizer. - View Dependent Claims (15, 16, 17)
whereby sensed common-mode voltages are compared to the target voltage to generate control voltages to differential buffers.
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17. The differential phase-locked loop of claim 15 wherein the first equalizer also receives the second sensed common-mode voltage, the first equalizer comparing the first sensed common-mode voltage to the second sensed common-mode voltage to generate a first control voltage applied to the first differential buffer to adjust the common-mode voltage of the first buffered pair carrying the differential buffered reference clock;
wherein the second equalizer also receives the first sensed common-mode voltage, the second equalizer comparing the second sensed common-mode voltage to the first sensed common-mode voltage to generate a second control voltage applied to the second differential buffer to adjust the common-mode voltage of the second buffered pair carrying the differential buffered feedback clock.
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18. A zero-delay buffer comprising:
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a differential reference clock carried over a first pair of differential lines, the differential reference clock having a first input common-mode voltage; a differential feedback clock carried over a second pair of differential lines, the differential feedback clock having a second input common-mode voltage wherein the first input common-mode voltage and the second input common-mode voltage are different voltages that can cause static phase offset; first differential buffer means, receiving the first pair carrying the differential reference clock, for generating a first buffered pair carrying a differential buffered reference clock; first differential-to-single-ended converter means, receiving the first buffered pair, for generating a first single-ended clock; second differential buffer means, receiving the second pair carrying the differential feedback clock, for generating a second buffered pair carrying a differential buffered feedback clock; second differential-to-single-ended converter means, receiving the second buffered pair, for generating a second single-ended clock; first common-mode sensor means, coupled to the first differential buffer means, for generating a first sensed common-mode voltage; second common-mode sensor means, coupled to the second differential buffer means, for generating a second sensed common-mode voltage; first equalizer means, receiving the first sensed common-mode voltage, for adjusting a common-mode voltage of the first buffered pair carrying the differential buffered reference clock in response to the first sensed common-mode voltage; phase compare means, receiving the first single-ended clock from the first differential-to-single-ended converter means, and receiving the second single-ended clock from the second differential-to-single-ended converter means, for generating a charge signal and a discharge signal in response to a phase difference between the first single-ended clock and the second single-ended clock; filter capacitor means for generating a sense voltage; charge means for charging the filter capacitor means in response to the charge signal from the phase compare means; discharge means for discharging the filter capacitor means in response to the discharge signal from the phase compare means; voltage-controlled oscillator means for generating the differential feedback clock having a frequency controlled by the sense voltage of the filter capacitor means; and first output differential clock buffer means, receiving the differential feedback clock, for driving a first differential buffered output clock, whereby static phase offset between the differential reference clock and the first differential buffered output clock caused by a difference in the first input common-mode voltage and the second input common-mode voltage is compensated for by the first equalizer means. - View Dependent Claims (19, 20)
whereby static phase offset between the first, second, third, and fourth differential buffered output clock is reduced by the first equalizer means compensating for differences in common-mode voltages.
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Specification