ARRAY SUBSTRATE OF LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE ARRAY SUBSTRATE

• US 20090135117A1
• Filed: 10/10/2008
• Published: 05/28/2009
• Est. Priority Date: 11/26/2007
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHO, Youngjoon
• Granted Patent: US 8,497,965 B2
• Time in Patent Office: Days
• US Class Current: 345/87
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

An array substrate of a liquid crystal display (LCD) device and a method of manufacturing the array substrate area disclosed. An array substrate of an LCD device includes an insulation substrate, a gate line, a data line, a thin film transistor connected to the gate line and the data line, a common electrode disposed at a pixel area, a pixel electrode overlapping with the common electrode, and a common line. The common line is connected to the common electrode and overlaps with a gap between the common electrode and the data line.

Claims

1. An array substrate of a liquid crystal display device, comprising:

an insulation substrate;

a gate line;

a data line;

a thin film transistor connected to the gate line and the data line;

a common electrode disposed at a pixel area;

a pixel electrode overlapping with the common electrode; and

a common line connected to the common electrode and overlapping with a gap between the common electrode and the data line.

2. The array substrate of claim 1, wherein the common electrode has a plate shape, and

wherein the pixel electrode comprises horizontal parts having a stripe shape and a vertical part disposed between the horizontal parts and connecting the horizontal parts.

3. The array substrate of claim 2, wherein the vertical part connects end portions of the horizontal parts.

4. The array substrate of claim 3, wherein the vertical part is arranged in a straight line.

5. The array substrate of claim 3, wherein the vertical part shifts back and forth from left to right.

6. The array substrate of claim 2, wherein the vertical part crosses the horizontal parts and connects adjacent horizontal parts.

7. The array substrate of claim 6, wherein the vertical part is arranged in a straight line.

8. The array substrate of claim 6, wherein the vertical part shifts back and forth from left to right.

9. The array substrate of claim 1, wherein the common line and the gate line are arranged on substantially the same layer.

10. The array substrate of claim 1, wherein the thin film transistor comprises:

a gate electrode;

an activation layer disposed on the gate electrode and insulated from the gate electrode; and

a source electrode and a drain electrode spaced apart from each other on the activation layer.

11. The array substrate of claim 1, wherein the gate line and the data line comprise at least one metal or alloy of metal selected from the group consisting of molybdenum (Mo), niobium (Nb), copper (Cu), aluminum (Al), chrome (Cr), silver (Ag), and tungsten (W).

12. The array substrate of claim 1, wherein the common line comprises at least one metal or alloy of metal selected from the group consisting of molybdenum (Mo), niobium (Nb), copper (Cu), aluminum (Al), chrome (Cr), silver (Ag), and tungsten (W).

13. The array substrate of claim 1, wherein the common electrode and the pixel electrode comprise a transparent conductive material.

14. The array substrate of claim 13, wherein the transparent conductive material comprises at least one material selected from the group consisting of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).

15. A method of manufacturing an array substrate of a liquid crystal display device, comprising:

forming a common electrode at each of a plurality of pixel areas of an insulation substrate;

forming a first metallic pattern comprising a gate line, a gate electrode, and a common line, the common line connected to the common electrode and covering a lateral gap between the common electrode and an adjacent common electrode;

forming a gate insulation layer on the first metallic pattern;

forming an activation layer on the gate insulation layer to overlap with the gate electrode;

forming a second metallic pattern comprising a data line overlapping with the common line and a source electrode and a drain electrode spaced apart from each other on the activation layer;

forming a protective layer on the second metallic pattern; and

forming a pixel electrode on the protective layer.

16. The method of claim 15, wherein the common electrode has as a plate shape, and

the pixel electrode comprises horizontal parts having stripe shapes and a vertical part disposed between adjacent horizontal parts to connect to the adjacent horizontal parts.

17. The method of claim 16, wherein the vertical part connects end portions of the horizontal parts, and

wherein the vertical part is arranged in a straight line.

18. The method of claim 16, wherein the vertical part connects end portions of the horizontal parts, and

wherein the vertical part shifts back and forth from left to right.

19. The method of claim 16, wherein the vertical parts cross the horizontal parts and connect adjacent horizontal parts, and

wherein the vertical part is arranged in a straight line.

20. The method of claim 16, wherein the vertical parts cross the horizontal parts and connect adjacent horizontal parts, and

wherein the vertical part shifts back and forth from left to right.