OPERATION SEQUENCE AND COMMANDS FOR MEASURING THRESHOLD VOLTAGE DISTRIBUTION IN MEMORY

• US 20090135646A1
• Filed: 11/26/2007
• Published: 05/28/2009
• Est. Priority Date: 11/26/2007
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Trinh, Cuong, Shlick, Mark, Lasser, Menahem, Murin, Mark
• Granted Patent: US 7,613,045 B2
• Time in Patent Office: Days
• US Class Current: 365/185.200
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells

Abstract

A memory device generates one or more read reference voltages rather than being explicitly supplied with each read reference voltage from an external host controller. The technique involves providing a command to the memory device that causes a reading of a set of storage elements by the memory device using a reference voltage which is different than a reference voltage used in a previous reading, where the new read reference value is not explicitly set outside the memory device. In one implementation, the memory device is provided with an initial reference voltage and a step size for generating additional reference voltages. The technique can be used, e.g., in determining a threshold voltage distribution of a set of storage elements. In this case, a voltage sweep can be applied to a word line associated with the set of storage elements, and data obtained based on the number of conductive storage elements.

Claims

1. A method for operating a memory device, comprising:

receiving, at the memory device, a first command;

in response to the first command, reading a set of storage elements in the memory device using a first read reference value but no other read reference value;

subsequent to said reading, receiving, at the memory device, a second command; and

in response to the second command, reading the set of storage elements using a second read reference value but no other read reference value, the memory device generates the second read reference value without receiving information for generating the second read reference value from outside the memory device subsequent to the receiving of the first command.

2. The method of claim 1, further comprising:

reading the set of storage elements a plurality of times, each time using a corresponding read reference value, the memory device generates the corresponding read reference values without receiving any information for generating the corresponding read reference values from outside the memory device subsequent to the receiving of the first command.

3. The method of claim 1, further comprising:

determining a threshold voltage distribution of the set of storage elements based, at least in part, on the reading using the first read reference value and the reading using the second read reference value.

4. The method of claim 1, wherein:

the first command identifies a voltage step size, and the memory device generates the second read reference value based on the voltage step size and the first read reference value.

5. The method of claim 1, wherein:

the memory device is pre-configured with a voltage step size, and the memory device generates the second read reference value based on the voltage step size and the first read reference value.

6. The method of claim 1, wherein:

the first command specifies the first read reference value.

7. The method of claim 1, wherein:

the first and second commands are received at the memory device from an external host controller.

8. The method of claim 7, wherein:

the memory device and the set of storage elements are on a memory die, and the external host controller is external to the memory die.

9. A method for operating a memory device, comprising:

receiving, at the memory device, a first command;

in response to the first command, reading a set of storage elements in the memory device using a first read reference value;

subsequent to said reading, receiving, at the memory device, a second command; and

in response to the second command, reading the set of storage elements using a second read reference value, the memory device generates the second read reference value without receiving information for generating the second read reference value from outside the memory device subsequent to the receiving of the first command; and

determining, based at least in part on the readings using the first and second read reference values, a threshold voltage distribution of the set of storage elements.

10. The method of claim 9, further comprising:

reading the set of storage elements a plurality of times, each time using a corresponding read reference value, the memory device generates the corresponding read reference values without receiving any information for generating the corresponding read reference values from outside the memory device subsequent to the receiving of the first command.

11. The method of claim 9, wherein:

the first command identifies a voltage step size, and the memory device generates the second read reference value based on the voltage step size and the first read reference value.

12. The method of claim 9, wherein:

the memory device is pre-configured with a voltage step size, and the memory device generates the second read reference value based on the voltage step size and the first read reference value.

13. The method of claim 9, wherein:

the first command specifies the first read reference value.

14. The method of claim 9, wherein:

the first and second commands are received at the memory device from an external host controller.

15. The method of claim 14, wherein:

the memory device and the set of storage elements are on a memory die, and the external host controller is external to the memory die.

16. A method for operating a memory device, comprising:

providing, from a host controller to a memory device, at least a first command, the memory device reads a set of storage elements using a first read reference value in response to the at least a first command;

subsequent to the providing the at least a first command, providing from the host controller to the memory device, at least a second command, the memory device reads the set of storage elements using a second read reference value in response to the at least a second command, the memory device generates the second read reference value without receiving information for generating the second read reference value from the host controller subsequent to the receiving of the at least a first command; and

determining, based at least in part on the readings using the first and second read reference values, a threshold voltage distribution of the set of storage elements.

17. The method of claim 16, wherein:

the at least a first command includes the first read reference value.

18. The method of claim 16, wherein:

the determining is performed, at least in part, by the host controller.

19. The method of claim 16, wherein:

the at least a first command identifies a voltage step size which the memory device uses in generating the second read reference value from the first read reference value.

20. The method of claim 16, wherein:

upon completion of a current read operation, the host controller receives a signal from the memory device indicating that new data is available, the host controller obtains the new data and provides a continue command to the memory device in response to the signal, and the memory device begins a next read operation in response to the continue command.

21. The method of claim 20, wherein:

the host controller provides the continue command to the memory device before obtaining the new data, and the memory device begins the next read operation before the host controller completes obtaining the new data.

22. The method of claim 16, wherein:

the memory device and the set of storage elements are on a memory die, and the host controller is external to the memory die.

23. A storage system, comprising:

a set of storage elements in a memory device; and

at least one control circuit in the memory device, the at least one control circuit;

a) receives a first command, b) in response to the first command, reads the set of storage elements using a first read reference value but no other read reference value, c) subsequent to the reading, receives a second command, and d) in response to the second command, reads the set of storage elements using a second read reference value but no other read reference value, the at least one control circuit generates the second read reference value without receiving information for generating the second read reference value from outside the memory device subsequent to the receiving of the first command.

24. The storage system of claim 23, wherein:

the at least one control circuit reads the set of storage elements a plurality of times, each time using a corresponding read reference value, and generates the corresponding read reference values without receiving any information for generating the corresponding read reference values from outside the memory device subsequent to the receiving of the first command.

25. The storage system of claim 23, wherein:

a threshold voltage distribution of the set of storage elements is determined based, at least in part, on the reading using the first read reference value and the reading using the second read reference value.

26. The storage system of claim 23, wherein:

the first command identifies a voltage step size, and the memory device generates the second read reference value based on the voltage step size and the first read reference value.

27. The storage system of claim 23, wherein:

the memory device is pre-configured with a voltage step size, and the memory device generates the second read reference value based on the voltage step size and the first read reference value.

28. The storage system of claim 23, wherein:

the first command specifies the first read reference value.

29. The storage system of claim 23, wherein:

the first and second commands are received at the at least one control circuit from an external host controller.

30. The storage system of claim 29, wherein:

the memory device and the set of storage elements are on a memory die, and the external host controller is external to the memory die.

31. A storage system, comprising:

a set of storage elements in a memory device; and

at least one control circuit in the memory device, the at least one control circuit;

a) receives a first command, b) in response to the first command, reads the set of storage elements using a first read reference value, c) subsequent to the reading, receives a second command, and d) in response to the second command, reads the set of storage elements using a second read reference value, the at least one control circuit generates the second read reference value without receiving information for generating the second read reference value from outside the memory device subsequent to the receiving of the first command, and a threshold voltage distribution of the set of storage elements is determined, based at least in part on the readings using the first and second read reference values.

32. The storage system of claim 31, wherein:

the at least one control circuit reads the set of storage elements a plurality of times, each time using a corresponding read reference value, and generates the corresponding read reference values without receiving any information for generating the corresponding read reference values from outside the memory device subsequent to the receiving of the first command.

33. The storage system of claim 31, wherein:

the first command identifies a voltage step size, and the memory device generates the second read reference value based on the voltage step size and the first read reference value.

34. The storage system of claim 31, wherein:

the memory device is pre-configured with a voltage step size, and the memory device generates the second read reference value based on the voltage step size and the first read reference value.

35. The storage system of claim 31, wherein:

the first command specifies the first read reference value.

36. The storage system of claim 31, wherein:

the first and second commands are received at the at least one control circuit from an external host controller.

37. The storage system of claim 36, wherein:

the memory device and the set of storage elements are on a memory die, and the external host controller is external to the memory die.

38. A storage system, comprising:

a host controller in communication with a memory device;

the host controller providing to the memory device at least a first command, the memory device reads an associated set of storage elements using a first read reference value in response to the at least a first command;

subsequent to the providing the at least a first command, the host controller provides to the memory device at least a second command, the memory device reads the set of storage elements using a second read reference value in response to the at least a second command, the memory device generates the second read reference value without receiving information for generating the second read reference value from the host controller subsequent to the receiving of the at least a first command; and

a threshold voltage distribution of the set of storage elements is determined, based at least in part on the readings using the first and second read reference values.

39. The storage system of claim 38, wherein:

the at least a first command includes the first read reference value.

40. The storage system of claim 38, wherein:

the threshold voltage distribution of the set of storage elements is determined, at least in part, by the host controller.

41. The storage system of claim 38, wherein:

the at least a first command identifies a voltage step size which the memory device uses in generating the second read reference value from the first read reference value.

42. The storage system of claim 38, wherein:

upon completion of a current read operation, the host controller receives a signal from the memory device indicating that new data is available, the host controller obtains the new data and provides a continue command to the memory device in response to the signal, and the memory device begins a next read operation in response to the continue command.

43. The storage system of claim 42, wherein:

the host controller provides the continue command to the memory device before obtaining the new data, and the memory device begins the next read operation before the host controller completes obtaining the new data.

44. The storage system of claim 38, wherein:

the memory device and the set of storage elements are on a memory die, and the host controller is external to the memory die.