COMPENSATION OF BACK PATTERN EFFECT IN A MEMORY DEVICE

• US 20090135650A1
• Filed: 04/23/2008
• Published: 05/28/2009
• Est. Priority Date: 11/28/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Vali, Tommaso, Moschiano, Violante, Santin, Giovanni
• Granted Patent: US 7,936,606 B2
• Time in Patent Office: Days
• US Class Current: 365/185.90
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.

Claims

1. A method for generating back pattern effect compensation in a memory device, the method comprising:

measuring a back pattern effect level in a series string of memory cells;

generating an indication of the back pattern effect level; and

compensating a read operation of the series string of memory cells in response to the indication.

2. The method of claim 1 wherein the indication is a series of bits such that each bit indicates a different time of discharge of a bit line coupled to the series string of memory cells.

3. The method of claim 1 wherein generating the indication comprises generating a plurality of bits wherein each bit indicates a discharge state of a bit line coupled to the series string of memory cells.

4. The method of claim 1 wherein measuring the back pattern effect level comprises generating a bit line current with a read operation.

5. The method of claim 1 wherein the memory device is a NAND flash memory device.

6. The method of claim 1 and further including:

performing a read operation that comprises biasing all word lines in the series string of memory cells, from a selected word line to a word line closest to a select gate drain line, with a first bias voltage; and

biasing all word lines below the selected word line with a second bias voltage that is greater than the first bias voltage.

7. A method for generating back pattern effect compensation in a non-volatile memory device, the method comprising:

performing a sense operation on a series string of memory cells that is coupled to a bit line such that a bit line current is generated;

generating a multiple bit word wherein each bit indicates a discharge status of the bit line during a different time period such that each bit is generated independently after each time period;

reading a selected memory cell of the series string of memory cells; and

compensating the reading in response to the multiple bit word wherein an increasing amount of back pattern effect results in a reduction of reading sense time.

8. The method of claim 7 wherein generating the multiple bit word comprises generating a strobe signal that controls output of each bit of the multiple bit word from the series string of memory cells.

9. The method of claim 8 and further including latching each bit of the multiple bit word into a latch after each time period.

10. The method of claim 9 and further comprising generating an enable signal after each strobe signal wherein the enable signal initiates the latching of each bit.

11. The method of claim 8 wherein each series string of memory cells is comprised of N latches and generating the multiple bit word further comprises generating N strobe signals.

12. A method for compensating a read operation for back pattern effects in a NAND flash memory device having a plurality of series strings of memory cells each coupled to a bit line, each series string coupled to N latches, the method comprising:

performing a read operation on a first series string of memory cells to generate a bit line current, the read operation comprising;

biasing each word line from a selected word line to a word line closest to a select gate drain line with a first voltage; and

biasing each word line below the selected word line to the word line closest to a select gate source line with a second voltage that is greater than the first voltage;

generating N strobe signals to enable a control transistor between the N latches and the series string of memory cells such that N bit line discharge status output signals are produced;

generating N enable signals to latch each of the N bit line discharge status output signals into the N latches to produce a back pattern effect level indication; and

adjusting a read time during a subsequent read operation in response to the back pattern effect level indication.

13. The method of claim 12 wherein adjusting the read time comprises decreasing the read time in response to higher levels of back pattern effects.

14. The method of claim 12 wherein N represents a discrete value of different steps of back pattern effect.

15. A solid state memory device comprising:

an array of memory cells organized in rows of memory cells coupled to word lines and series strings of memory cells coupled to bit lines; and

a set of N latches coupled to each series string of memory cells, wherein each set of latches is adapted to store an indication of a back pattern effect experienced by its respective series string of memory cells.

16. The memory device of claim 15 and further comprising a control transistor that couples each set of N latches to each series string of memory cells.

17. The memory device of claim 15 and further comprising memory control circuitry coupled to the array of memory cells for generating a series of N enable signals that latch each of N bits into its respective latch.

18. The memory device of claim 15 and further comprising a processor external to the memory device and coupled to the memory device for controlling operation of a resulting memory system.

19. The memory device of claim 17 wherein the memory control circuitry is adapted to generate N strobe signals, each strobe signal enabling a control transistor that couples a set of N latches to its respective series string of memory cells.

20. The memory device of claim 15 wherein the indication of the back pattern effect comprises a multiple bit word wherein each bit comprises a bit line discharge status indication of its respective bit line.