FATIGUE MANAGEMENT SYSTEM AND METHOD FOR HYBRID NONVOLATILE SOLID STATE MEMORY SYSTEM

• US 20090138654A1
• Filed: 02/04/2009
• Published: 05/28/2009
• Est. Priority Date: 12/11/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Pantas
• Granted Patent: US 9,153,337 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A solid state memory system comprises a first nonvolatile semiconductor memory having a first write cycle lifetime and a first set of physical addresses, and a second nonvolatile semiconductor memory having a second write cycle lifetime and a second set of physical addresses. The first write cycle lifetime is greater than the second write cycle lifetime. The system further comprises a fatigue management module to generate a write frequency ranking for a plurality of logical addresses. The fatigue management module maps each of the plurality of logical addresses to a physical address of the first set of physical addresses or the second set of physical addresses based on the write frequency rankings.

Claims

1. A solid state memory system, comprising:

a first nonvolatile semiconductor memory having a first write cycle lifetime and a first set of physical addresses;

a second nonvolatile semiconductor memory having a second write cycle lifetime and a second set of physical addresses, wherein the first write cycle lifetime is greater than the second write cycle lifetime; and

a fatigue management module to

generate a write frequency ranking for a plurality of logical addresses; and

map each of the plurality of logical addresses to a physical address of the first set of physical addresses or the second set of physical addresses based on the write frequency rankings.

2. The system of claim 1, wherein the write frequency ranking for one of the plurality of logical addresses is based on a number of write operations to the one of the plurality of logical addresses.

3. The system of claim 1, wherein the write frequency ranking for one of the plurality of logical addresses is based on a number of write operations to the one of the plurality logical addresses during a predetermined period.

4. The system of claim 1, wherein the write frequency ranking for one of the plurality of logical addresses is based on a time averaged write count for the one of the plurality of logical addresses.

5. The system of claim 4, wherein the time averaged write count is based on:

WCA(n+1)=WCA(n)*d+WE(n)*a,

where WCA(n) is the time averaged write count at timestep n;

WE(n) is an actual write event at timestep n, such that WE(n) equals 1 if a write event occurred at timestep n and otherwise equals 0;

d is a first constant; and

a is a second constant.

6. The system of claim 1, further comprising a wear leveling module, wherein the wear leveling module:

generates a first wear level for the first nonvolatile semiconductor memory based on the first write cycle lifetime; and

generates a second wear level for the second nonvolatile semiconductor memory based on the second write cycle lifetime,

wherein the mapping of the plurality of logical addresses is further based on the first wear level and the second wear level.

7. The system of claim 1, wherein a lowest write frequency rating of the logical addresses that are mapped to the first nonvolatile semiconductor memory is greater than a highest write frequency rating of the logical addresses that are mapped to the second nonvolatile semiconductor memory.

8. A fatigue management method for a solid state memory system, comprising:

providing a first nonvolatile semiconductor memory having a first write cycle lifetime and a first set of physical addresses;

providing a second nonvolatile semiconductor memory having a second write cycle lifetime and a second set of physical addresses, wherein the first write cycle lifetime is greater than the second write cycle lifetime;

generating a write frequency ranking for a plurality of logical addresses; and

mapping each of the plurality of logical addresses to a physical address of the first set of physical addresses or the second set of physical addresses based on the write frequency rankings.

9. The method of claim 8, wherein the write frequency ranking for one of the plurality of logical addresses is based on a number of write operations to the one of the plurality of logical addresses.

10. The method of claim 8, wherein the write frequency ranking for one of the plurality of logical addresses is based on a number of write operations to the one of the plurality logical addresses during a predetermined period.

11. The method of claim 8, wherein the write frequency ranking for one of the plurality of logical addresses is based on a time averaged write count for the one of the plurality of logical addresses.

12. The method of claim 11, wherein the time averaged write count is based on:

WCA(n+1)=WCA(n)*d+WE(n)*a,

where WCA(n) is the time averaged write count at timestep n;

WE(n) is an actual write event at timestep n, such that WE(n) equals 1 if a write event occurred at timestep n and otherwise equals 0;

d is a first constant; and

a is a second constant.

13. The method of claim 8, further comprising:

generating a first wear level for the first nonvolatile semiconductor memory based on the first write cycle lifetime; and

generating a second wear level for the second nonvolatile semiconductor memory based on the second write cycle lifetime,

wherein the mapping of the plurality of logical addresses is further based on the first wear level and the second wear level.

14. The method of claim 8, wherein a lowest write frequency rating of the logical addresses that are mapped to the first nonvolatile semiconductor memory is greater than a highest write frequency rating of the logical addresses that are mapped to the second nonvolatile semiconductor memory.