Dynamic instruction execution using distributed transaction priority registers

• US 20090138683A1
• Filed: 11/28/2007
• Published: 05/28/2009
• Est. Priority Date: 11/28/2007
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bell, Robert H. JR., Capps, Louis B. JR.
• Application Number:
  US11/946,615
• Publication Number:
  US 20090138683A1
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values in thread priority registers distributed throughout the computer system, instructions from different threads that are dispatched through the system are allocated system resources based on the priority values assigned to the respective instruction threads. Priority values for individual threads may be updated with control software which tests thread performance and uses the test results to apply predetermined adjustment policies. The test results may be used to optimize the workload allocation of system resources by dynamically assigning thread priority values to individual threads using any desired policy, such as achieving thread execution balance relative to thresholds and to performance of other threads, reducing thread response time, lowering power consumption, etc.

Claims

1. A method for prioritizing instructions in a data processing system comprising:

assigning a first priority value to a first instruction thread and a second priority value to a second instruction thread;

storing the first and second priority values in at least a first thread priority register in the data processing system;

replicating the first and second priority values in a plurality of thread priority registers located in a corresponding plurality of hardware resources in the data processing system;

presenting a request from a first instruction in the first instruction thread to access a first hardware resource; and

allocating the first hardware resource to the first instruction from the first instruction thread based on the first priority value.

2. The method of claim 1, where replicating the first and second priority values in a plurality of thread priority registers comprises allocating a plurality of thread priority registers in hardware for every thread that can execute in the data processing system.

3. The method of claim 1, where replicating the first and second priority values comprises lazily propagating priority values from the first thread priority register through the plurality of thread priority registers.

4. The method of claim 1, where the first hardware resource comprises an L1 cache memory, L2 cache memory, L3 cache memory, memory controller, execution unit or interconnection bus.

5. The method of claim 1, where allocating the first hardware resource comprises selecting a core load or prefetch request from the first instruction thread to be performed before performing a request from another instruction thread.

6. The method of claim 1, further comprising:

monitoring performance status information for at least the first instruction thread; and

adjusting at least the first priority value based on the performance status information.

7. The method of claim 6, where adjusting at least the first priority value comprises applying a policy to achieve thread execution balance between the first instruction thread and at least one additional instruction thread.

8. The method of claim 6, where monitoring performance status information comprises measuring a cycles per instruction parameter, a cache miss parameter, a branch predictability parameter, a core stall parameter, a prefetch hit parameter, a load/store frequency parameter, an FXU instruction parameter, an FPU instruction parameter, an application indicator parameter or a core utilization parameter.

9. A computer-usable medium embodying computer program code, the computer program code comprising computer executable instructions configured for prioritizing instructions in a data processing system by:

assigning a first priority value to a first instruction thread and a second priority value to a second instruction thread;

storing the first and second priority values in at least a first thread priority register in the data processing system;

replicating the first and second priority values in a plurality of thread priority registers located in a corresponding plurality of hardware resources in the data processing system;

presenting a request from a first instruction in the first instruction thread to access a first hardware resource; and

allocating the first hardware resource to the first instruction from the first instruction thread based on the first priority value.

10. The computer-usable medium of claim 9, further comprising computer executable instructions configured for prioritizing instructions in a data processing system by allocating a plurality of thread priority registers in hardware for every thread that can execute in the data processing system.

11. The computer-usable medium of claim 9, further comprising computer executable instructions configured for prioritizing instructions in a data processing system by lazily propagating priority values from the first thread priority register through the plurality of thread priority registers.

12. The computer-usable medium of claim 9, where the first hardware resource comprises an L1 cache memory, L2 cache memory, L3 cache memory, memory controller, execution unit or interconnection bus.

13. The computer-usable medium of claim 9, where allocating the first hardware resource comprises selecting a core load or prefetch request from the first instruction thread to be performed before performing a request from another instruction thread.

14. The computer-usable medium of claim 9, further comprising computer executable instructions configured for prioritizing instructions in a data processing system by:

monitoring performance status information for at least the first instruction thread; and

adjusting at least the first priority value based on the performance status information.

15. The computer-usable medium of claim 14, where adjusting at least the first priority value comprises applying a policy to achieve thread execution balance between the first instruction thread and at least one additional instruction thread.

16. The computer-usable medium of claim 14, where monitoring performance status information comprises measuring a cycles per instruction parameter, a cache miss parameter, a branch predictability parameter, a core stall parameter, a prefetch hit parameter, a load/store frequency parameter, an FXU instruction parameter, an FPU instruction parameter, an application indicator parameter or a core utilization parameter.

17. A data processing system comprising:

a processor for executing a plurality of instruction threads, said processor comprising

one or more processor resources, such as a cache memory, memory controller, interconnect bus or interconnect controller;

a thread priority register located at one or more processor resources; and

a computer-usable medium embodying computer program code, the computer-usable medium being coupled to the data bus, the computer program code comprising instructions for prioritizing instructions in the data processing system by;

assigning a first priority value to a first instruction thread and a second priority value to a second instruction thread;

storing the first and second priority values in at least a first thread priority register in the data processing system;

replicating the first and second priority values in a plurality of thread priority registers located in a corresponding plurality of hardware resources in the data processing system;

presenting a request from a first instruction in the first instruction thread to access a first processor resource; and

allocating the first processor resource to the first instruction from the first instruction thread based on the first priority value.

18. The data processing system of claim 17, further comprising instructions for prioritizing instructions in the data processing system by allocating a plurality of thread priority registers in hardware for every thread that can execute in the data processing system.

19. The data processing system of claim 17, further comprising instructions for prioritizing instructions in the data processing system by lazily propagating priority values from the first thread priority register through the plurality of thread priority registers.

20. The data processing system of claim 17, where the processor comprises one or more processor cores, where each processor core processes two or more instruction threads.