APPARATUS AND METHOD FOR MICRO PERFORMANCE TUNING OF A CLOCKED DIGITAL SYSTEM

• US 20090138748A1
• Filed: 11/28/2007
• Published: 05/28/2009
• Est. Priority Date: 11/28/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kim, Jonghae, Kim, Moon J., Moulic, James R., Kim, Daeik
• Granted Patent: US 8,037,340 B2
• Time in Patent Office: Days
• US Class Current: 713/503
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency

Abstract

An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, the clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period. The apparatus further including at least one voltage drop sensor coupled to the core, the sensor being configured to generate an output signal for detecting a voltage drop in the core and to determine whether or not the output signal is detected within the clock period and, if the output signal is not detected, the sensor dynamically adjusts the clock period of the clock signal provided to the core to allow more time to complete state transitions, such that, dynamically adjusting the clock period effectively changes an effective core clock frequency.

Claims

1. An apparatus for micro-tuning an effective clock frequency of a core in a microprocessor, comprising:

a microprocessor including at least one core, said at least one core comprising logic that is configured to transition between states;

a clock signal coupled to said microprocessor, said clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period, said predetermined clock period being an inverse of said predetermined clock frequency; and

at least one sensor coupled to said at least one core in said microprocessor, said at least one sensor being configured to generate a sensor output signal for detecting at least one level of voltage drop in said at least one core when said logic within said at least one core is transitioning between states, said at least one sensor being configured to determine whether or not said sensor output signal generated is detected within said predetermined clock period, wherein if said sensor output signal generated is not detected within said predetermined clock period, said at least one sensor dynamically adjusts said predetermined clock period of said clock signal to allow said at least one core more time to complete said transitioning between states, and wherein dynamically adjusting said predetermined clock period effectively changes an effective clock frequency of said at least one core in said microprocessor.

2. The apparatus according to claim 1, wherein said at least one sensor dynamically adjusts said clock period within an order of one clock cycle.

3. The apparatus according to claim 2, wherein said at least one sensor comprises an embedded delay line of logic gates.

4. The apparatus according to claim 3, wherein if said sensor output signal generated is not detected before a clock falling edge of said clock signal, said at least one sensor triggers adjustment of said predetermined clock period at said clock falling edge of said clock signal to provide more time to said at least one core in said microprocessor to complete said transition between states, and wherein said effective clock frequency of said at least one core in said microprocessor is adjusted.

5. The apparatus according to claim 4, wherein if said sensor output signal generated is detected before said clock falling edge of said clock signal, said at least one sensor does not trigger adjustment of said predetermined clock period at said clock falling edge of said clock signal, and wherein said effective clock frequency of said at least one core in said microprocessor remains unadjusted.

6. The apparatus according to claim 5, wherein said effective clock frequency for said at least one core is calculated based on an average clock period calculated for said at least one core using a sum of dynamically adjusted and unadjusted clock periods, said effective clock frequency being faster than said worst-case clock frequency, and wherein said respective clock period is dynamically adjusted by said at least one sensor by an order comprising at least one of:

a clock cycle, a multiple of said clock cycle and an integer fraction of said clock cycle.

7. An apparatus for improving performance of a synchronous digital system, comprising:

a synchronous digital system including an integrated circuit comprised of a plurality of cores;

a respective power supply configured to supply a respective voltage to a respective core of said plurality of cores of said integrated circuit;

a clock signal source having a clock signal input coupled to said synchronous digital system and a clock signal output coupled to said integrated circuit, said clock signal source having a predetermined clock frequency and a predetermined clock period, said predetermined clock frequency being based on a worst-case clock frequency and being configured to set forth a respective effective core frequency at which said respective core of said plurality of cores performs circuit transitions; and

one or more sensors coupled to said respective core of said plurality of cores of said integrated circuit, said one or more sensors being configured to detect a respective level of voltage drop in a respective core caused by a time delay in performing a circuit transition and being configured to determine whether said respective level of voltage drop detected in said respective core necessitates an adjustment in a respective clock period of said clock signal output and, if so, said sensor dynamically adjusts said respective clock period of said clock signal output to provide a non-standard transition time to said respective core for completing said circuit transition.

8. The apparatus according to claim 7, wherein said respective clock period is dynamically adjusted by a sensor of said one or more sensors by an order comprising at least one of:

a clock cycle, a multiple of said clock cycle and an integer fraction of said clock cycle.

9. The apparatus according to claim 8, wherein said sensor of said one or more sensors comprises an embedded delay line of logic gates.

10. The apparatus according to claim 9, wherein a respective sensor of said one or more is configured to generate a sensor output signal for detecting said at least one level of voltage drop in said respective core caused by said time delay in performing said circuit transition, said respective sensor being further configured to determine whether or not said sensor output signal generated is detected within said predetermined clock period, wherein if said sensor output signal generated is not detected within said predetermined clock period, said respective sensor dynamically adjusts said predetermined clock period of said clock signal to allow said respective core more time to complete said circuit transition, and wherein dynamically adjusting said predetermined clock period effectively changes an effective clock frequency of said respective core in said microprocessor.

11. The apparatus according to claim 10, wherein if said sensor output signal generated arrives before said clock falling edge of said clock signal, said respective sensor does not trigger adjustment of said predetermined clock period at said clock falling edge of said clock signal and said respective sensor maintains said respective clock period of said clock signal output, and wherein said effective clock frequency of said respective core remains unadjusted.

12. The apparatus according to claim 11, wherein said respective sensor is configured to monitor said clock rising edge and said clock falling edge of said clock signal and dynamically adjusts said predetermined clock period at said clock falling edge to provide more time to said respective core to complete said circuit transition.

13. The apparatus according to claim 12, wherein said respective effective core frequency for said respective core is calculated based on an average clock period calculated for said respective core using a sum of dynamically adjusted and unadjusted clock periods, said respective effective clock frequency being faster than said worst-case clock frequency, and wherein said respective clock period is dynamically adjusted by said respective sensor by an order comprising at least one of:

a clock cycle, a multiple of said clock cycle and an integer fraction of said clock cycle.

14. A method for optimizing performance of a microprocessor, said method comprising the steps of:

providing a microprocessor having at least one core, said microprocessor being coupled to an adjustable clock source configured to supply a clock signal to said at least one core, said clock signal having a predetermined clock frequency based on a worst-case clock frequency, said predetermined clock frequency being an inverse of a predetermined clock period;

connecting a local voltage power source to said at least one core in said microprocessor;

supplying at least one sensor coupled to said at least one core and configured to detect a change in voltage levels in said at least one core, when said at least one core in said microprocessor is transitioning between states; and

dynamically adjusting, based on an output signal generated by said at least one sensor supplied, said predetermined clock period of said adjustable clock source to allow a non-standard time to said at least one core to complete transitioning between states, wherein an effective core frequency of said at least one core is optimized, and wherein performance of said microprocessor is optimized.

15. The method according to claim 14, further comprising the step of:

utilizing at least one decoupling capacitor coupled to said at least one core, said at least one decoupling capacitor being configured to filter out any sudden change in voltage levels in said local voltage power source supplied to said at least one core and being configured to function as a local battery to provide power to said at least one core in said microprocessor when necessary, wherein said any sudden change in voltage level comprises at least one of;

a drop in power supply voltage and a bounce in ground voltage.

16. The method according to claim 15, wherein said at least one sensor comprises an embedded delay line of logic gates.

17. The method according to claim 16, wherein said at least one sensor is configured to determine whether or not said sensor output signal generated is detected within said predetermined clock period, wherein if said sensor output signal generated is not detected within said predetermined clock period, said at least one sensor dynamically adjusts said predetermined clock period of said clock signal to allow said at least one core more time to complete said transitioning between states, and wherein if said sensor output signal generated is detected within said predetermined clock period, said at least one sensor does not trigger adjustment of said predetermined clock period, and wherein said effective clock frequency of said at least one core remains unadjusted.

18. The method according to claim 17, wherein said dynamically adjusting step further comprises the step of:

dynamically adjusting said clock period by an order comprising at least one of;

a clock cycle, a multiple of said clock cycle and an integer fraction of said clock cycle.

19. The method according to claim 18, further comprising the steps of:

providing a microprocessor having at least two cores;

connecting a separate local voltage power source to a respective core of said at least two cores in said microprocessor;

supplying at least two sensors, a respective sensor of said at least two sensors being coupled to a respective core of said at least two cores, said respective sensor being configured to detect a change in voltage levels in said respective core of said at least two cores when said respective core in said microprocessor is transitioning between states; and

dynamically adjusting, based on an output signal from said respective sensor supplied, said predetermined clock period of said adjustable clock source to allow a non-standard time to said respective core to complete transitioning between states, wherein an effective core frequency of said respective core is optimized, and wherein performance of said microprocessor is optimized.

20. A method for optimizing performance of a clocked digital system, said method comprising the steps of:

providing a multi-core clocked digital system having a plurality of cores, said multi-core clocked digital system being coupled to an adjustable clock source configured to supply a clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period, said predetermined clock period being an inverse of said predetermined clock frequency;

supplying a separate local voltage power source to each respective core of said plurality of cores within said multi-core clocked digital system;

coupling a respective decoupling capacitor to said each respective core of said plurality of cores, said respective decoupling capacitor being configured to filter out sudden changes in voltage levels in said separate local voltage power source supplied to said each respective core and being configured to function as a local battery to provide power to said each respective core in said multi-core clocked digital system when necessary;

connecting at least one sensor to said each respective core, said at least one sensor being configured to detect at least one level of voltage drop caused by a state transition of said each respective core in said multi-core clocked digital system; and

dynamically adjusting, based on an output signal generated by said at least one sensor connected to a respective core, a clock period of said adjustable clock source for said respective core for completing said state transition, wherein performance of said clocked digital system is optimized via an adjustment in an effective frequency of said respective core.

21. The method according to claim 20, wherein said at least one sensor monitors a clock rising edge and a clock falling edge of said clock signal and triggers adjustment of said clock period at said clock falling edge to provide more time to said respective core to complete said state transition.

22. The method according to claim 21, wherein said at least one sensor is configured to determine whether or not said sensor output signal generated is detected within said predetermined clock period, wherein if said sensor output signal generated is not detected within said predetermined clock period, said at least one sensor dynamically adjusts said predetermined clock period of said clock signal to allow said respective core more time to complete said transitioning between states, and wherein if said sensor output signal generated is detected within said predetermined clock period, said at least one sensor does not trigger adjustment of said predetermined clock period, and wherein said effective clock frequency of said respective core remains unadjusted.

23. The method according to claim 22, wherein said effective core frequency for said respective core is calculated based on an average clock period calculated for said core using a sum of dynamically adjusted and unadjusted clock periods, said effective core frequency being faster than said worst-case clock frequency.

24. The method according to claim 23, wherein said at least one sensor comprises an embedded delay line of logic gates.

25. The method according to claim 21, wherein said at least one sensor dynamically adjusts said clock period by an order comprising at least one of:

a clock cycle, a multiple of said clock cycle and an integer fraction of said clock cycle.