System and Method for Sequential Equivalence Checking for Asynchronous Verification

• US 20090138837A1
• Filed: 11/27/2007
• Published: 05/28/2009
• Est. Priority Date: 11/27/2007
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: International Business Machines Corporation
• Inventors: Ja, Yee, Paruthi, Viresh, Mony, Hari, Baumgartner, Jason R., Ramanandray, Barinjato
• Granted Patent: US 7,882,473 B2
• Time in Patent Office: Days
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking

Abstract

A system and method for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.

Claims

1. A method, in a data processing system, for performing asynchronous verification of an integrated circuit design, comprising:

receiving a first model of the integrated circuit design;

unfolding paths within the first model that have asynchronous crossings to generate an unfolded integrated circuit design model;

inserting asynchronous crossing logic into the unfolded integrated circuit design model to generate a second model;

correlating outputs of the first model with outputs of the second model;

applying one or more exclusive OR operations to the correlated outputs of the first model and the second model; and

performing sequential equivalence checking on the first model and second model utilizing the applied one or more exclusive OR operations.

2. The method of claim 1, further comprising:

determining, based on outputs of the one or more exclusive OR operations due to the sequential equivalence checking, whether the asynchronous crossings of the integrated circuit design are verified or not verified; and

generating an output indicative of whether the asynchronous crossings of the integrated circuit design are verified or not verified based on results of the determination.

3. The method of claim 2, further comprising:

performing a failure analysis to determine if a failure of the asynchronous crossings is a real failure or a false failure in response to determining that the asynchronous crossings of the integrated circuit design are not verified.

4. The method of claim 3, further comprising:

determining if results of the failure analysis indicate a false failure of the asynchronous crossings; and

generating an output indicating a real failure of the integrated circuit design and a need to modify the integrated circuit design if results of the failure analysis indicate a real failure occurred with the asynchronous crossings of the integrated circuit design.

5. The method of claim 3, further comprising:

determining if results of the failure analysis indicate a false failure of the asynchronous crossings; and

generating an output indicating a false failure of the integrated circuit design and a need to modify the sequential equivalence checking of the first model and second model if results of the failure analysis indicate a false failure occurred with the asynchronous crossings of the integrated circuit design.

6. The method of claim 1, wherein the asynchronous crossing logic comprises skewing logic for randomly selecting a phase difference between clocks of asynchronous domains of asynchronous crossings in the unfolded integrated circuit design.

7. The method of claim 6, wherein the asynchronous crossing logic further comprises, for an asynchronous bus in the unfolded integrated circuit design, transitioning bit detection logic for detecting transitioning bits of strands of the asynchronous bus, and maximum delay logic for determining a maximum delay of strands having transitioning bits in the asynchronous bus.

8. The method of claim 7, wherein inserting the asynchronous crossing logic further comprises:

replicating the second model to generate a third model; and

coupling, for the asynchronous bus in the second model, the maximum delay logic of the second model to random select inputs of the skewing logic associated with a corresponding asynchronous bus in the third model to thereby bypass the random select inputs.

9. An apparatus, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to;

receive a first model of the integrated circuit design;

unfold paths within the first model that have asynchronous crossings to generate an unfolded integrated circuit design model;

insert asynchronous crossing logic into the unfolded integrated circuit design model to generate a second model;

correlate outputs of the first model with outputs of the second model;

apply one or more exclusive OR operations to the correlated outputs of the first model and the second model; and

perform sequential equivalence checking on the first model and second model utilizing the applied one or more exclusive OR operations.

10. The apparatus of claim 9, wherein the instructions further cause the processor to:

determine, based on outputs of the one or more exclusive OR operations due to the sequential equivalence checking, whether the asynchronous crossings of the integrated circuit design are verified or not verified; and

generate an output indicative of whether the asynchronous crossings of the integrated circuit design are verified or not verified based on results of the determination.

11. The apparatus of claim 10, wherein the instructions further cause the processor to:

perform a failure analysis to determine if a failure of the asynchronous crossings is a real failure or a false failure in response to determining that the asynchronous crossings of the integrated circuit design are not verified.

12. The apparatus of claim 11, wherein the instructions further cause the processor to:

determine if results of the failure analysis indicate a false failure of the asynchronous crossings; and

generate an output indicating a real failure of the integrated circuit design and a need to modify the integrated circuit design if results of the failure analysis indicate a real failure occurred with the asynchronous crossings of the integrated circuit design.

13. The apparatus of claim 11, wherein the instructions further cause the processor to:

determine if results of the failure analysis indicate a false failure of the asynchronous crossings; and

generate an output indicating a false failure of the integrated circuit design and a need to modify the sequential equivalence checking of the first model and second model if results of the failure analysis indicate a false failure occurred with the asynchronous crossings of the integrated circuit design.

14. The apparatus of claim 9, wherein the asynchronous crossing logic comprises skewing logic for randomly selecting a phase difference between clocks of asynchronous domains of asynchronous crossings in the unfolded integrated circuit design.

15. The apparatus of claim 14, wherein the asynchronous crossing logic further comprises, for an asynchronous bus in the unfolded integrated circuit design, transitioning bit detection logic for detecting transitioning bits of strands of the asynchronous bus, and maximum delay logic for determining a maximum delay of strands having transitioning bits in the asynchronous bus.

16. The apparatus of claim 15, wherein inserting the asynchronous crossing logic further comprises:

replicating the second model to generate a third model; and

coupling, for the asynchronous bus in the second model, the maximum delay logic of the second model to random select inputs of the skewing logic associated with a corresponding asynchronous bus in the third model to thereby bypass the random select inputs.

17. A computer program product comprising a computer recordable medium having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:

receive a first model of the integrated circuit design;

unfold paths within the first model that have asynchronous crossings to generate an unfolded integrated circuit design model;

insert asynchronous crossing logic into the unfolded integrated circuit design model to generate a second model;

correlate outputs of the first model with outputs of the second model;

apply one or more exclusive OR operations to the correlated outputs of the first model and the second model; and

perform sequential equivalence checking on the first model and second model utilizing the applied one or more exclusive OR operations.

18. The computer program product of claim 17, wherein the computer readable program further causes the computing device to:

determine, based on outputs of the one or more exclusive OR operations due to the sequential equivalence checking, whether the asynchronous crossings of the integrated circuit design are verified or not verified; and

generate an output indicative of whether the asynchronous crossings of the integrated circuit design are verified or not verified based on results of the determination.

19. The computer program product of claim 18, wherein the computer readable program further causes the computing device to:

perform a failure analysis to determine if a failure of the asynchronous crossings is a real failure or a false failure in response to determining that the asynchronous crossings of the integrated circuit design are not verified.

20. The computer program product of claim 19, wherein the computer readable program further causes the computing device to:

determine if results of the failure analysis indicate a false failure of the asynchronous crossings; and

generate an output indicating a real failure of the integrated circuit design and a need to modify the integrated circuit design if results of the failure analysis indicate a real failure occurred with the asynchronous crossings of the integrated circuit design.

21. The computer program product of claim 19, wherein the computer readable program further causes the computing device to:

determine if results of the failure analysis indicate a false failure of the asynchronous crossings; and

generate an output indicating a false failure of the integrated circuit design and a need to modify the sequential equivalence checking of the first model and second model if results of the failure analysis indicate a false failure occurred with the asynchronous crossings of the integrated circuit design.

22. The computer program product of claim 17, wherein the asynchronous crossing logic comprises skewing logic for randomly selecting a phase difference between clocks of asynchronous domains of asynchronous crossings in the unfolded integrated circuit design.

23. The computer program product of claim 22, wherein the asynchronous crossing logic further comprises, for an asynchronous bus in the unfolded integrated circuit design, transitioning bit detection logic for detecting transitioning bits of strands of the asynchronous bus, and maximum delay logic for determining a maximum delay of strands having transitioning bits in the asynchronous bus.

24. The computer program product of claim 23, wherein inserting the asynchronous crossing logic further comprises:

replicating the second model to generate a third model; and

coupling, for the asynchronous bus in the second model, the maximum delay logic of the second model to random select inputs of the skewing logic associated with a corresponding asynchronous bus in the third model to thereby bypass the random select inputs.