DISPLAY DEVICE AND METHOD FOR MANUFACTURING THEREOF

• US 20090140270A1
• Filed: 11/25/2008
• Published: 06/04/2009
• Est. Priority Date: 11/30/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: OZAWA, Suguru, MURAKAMI, Satoshi, TAKAHASHI, Kei
• Granted Patent: US 8,148,236 B2
• Time in Patent Office: Days
• US Class Current: 257/88
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

An object is to provide a system-on-panel display device including a display portion and a peripheral circuit for controlling display on the display portion over one substrate, which can operate more accurately. The display device has a display portion provided with a pixel portion including a plurality of pixels and a peripheral circuit portion for controlling display on the display portion, which are provided over a substrate. Each of the display portion and the peripheral circuit portion includes a plurality of transistors. For semiconductor layers of the transistors, single crystal semiconductor materials are used.

Claims

1. A display device comprising:

a substrate;

a display portion comprising;

a pixel comprising a first transistor;

a scan line driver circuit connected to the pixel; and

a signal line driver circuit connected to the pixel;

a peripheral circuit portion comprising a second transistor,

wherein the first transistor comprises;

a first single crystal semiconductor layer formed over the substrate with a bonding layer interposed therebetween; and

a first gate electrode formed over the first single crystal semiconductor layer with a first gate insulating layer interposed therebetween, and

wherein the second transistor comprises;

a second single crystal semiconductor layer formed over the substrate with the bonding layer interposed therebetween; and

a second gate electrode formed over the second single crystal semiconductor layer with a second gate insulating layer interposed therebetween.

2. The display device according to claim 1,

wherein the first transistor further comprises a third gate insulating layer interposed between the first gate insulating layer and the first gate electrode.

3. The display device according to claim 1,

wherein the first transistor is driven so that |V_ds|=|V_gs|−

|V_th| is satisfied, under a condition that a voltage applied between the first gate electrode and a source terminal of the first transistor is V_gs, a voltage applied between the source terminal and a drain terminal is V_ds, and a threshold voltage of the first transistor is V_th.

4. The display device according to claim 1,

wherein the peripheral circuit portion comprises an arithmetic circuit, an image processing circuit, and a memory circuit, and

wherein the second transistor is comprised in any one of the arithmetic circuit, the image processing circuit, and the memory circuit.

5. A display device comprising:

a substrate;

a display portion comprising;

a pixel comprising;

a first transistor; and

a pixel electrode;

a scan line driver circuit connected to the pixel; and

a signal line driver circuit connected to the pixel;

a power supply circuit electrically connected to the pixel electrode via the first transistor;

a peripheral circuit portion comprising a second transistor,

wherein the first transistor comprises;

a first single crystal semiconductor layer formed over the substrate with a bonding layer interposed therebetween; and

a first gate electrode formed over the first single crystal semiconductor layer with a first gate insulating layer interposed therebetween,

wherein the second transistor comprises;

a second single crystal semiconductor layer formed over the substrate with the bonding layer interposed therebetween; and

a second gate electrode formed over the second single crystal semiconductor layer with a second gate insulating layer interposed therebetween,

wherein the pixel has a longer side and a shorter side,

wherein a channel length direction of the first transistor is parallel to the longer side, and

wherein 143≦

L≦

AX (0<

A≦

0.7, X≧

204) is satisfied under a condition that a channel length of the first transistor is L μ

m and a length of the longer side is X μ

m.

6. The display device according to claim 5,

wherein the first transistor further comprises a third gate insulating layer interposed between the first gate insulating layer and the first gate electrode.

7. The display device according to claim 5,

wherein the first transistor is driven so that |V_ds|=|V_gs|−

|V_th| is satisfied, under a condition that a voltage applied between the first gate electrode and a source terminal of the first transistor is V_gs, a voltage applied between the source terminal and a drain terminal is V_ds, and a threshold voltage of the first transistor is V_th.

8. The display device according to claim 5,

wherein the peripheral circuit portion comprises an arithmetic circuit, an image processing circuit, and a memory circuit, and

wherein the second transistor is comprised in any one of the arithmetic circuit, the image processing circuit, and the memory circuit.

9. The display device according to claim 5,

wherein the pixel further comprises:

an electroluminescent layer formed over the pixel electrode; and

a first electrode formed over the electroluminescent layer, and

wherein an amount of current flowing through the electroluminescent layer is larger than or equal to 0.1 μ

A and smaller than or equal to 1.0 μ

A.

10. A method for manufacturing a display device comprising the steps of:

doping an ion into a region in a first substrate, wherein the first substrate is a single crystal semiconductor substrate;

forming a bonding layer over the first substrate;

adhering the bonding layer to a second substrate, wherein the second substrate has an insulating surface;

forming a semiconductor layer over the second substrate with the bonding layer interposed therebetween, by cleaving the first substrate using the region as a cleavage plane;

forming a first semiconductor island and a second semiconductor island, by etching the semiconductor layer;

forming a gate insulating layer over the first semiconductor island and over the second semiconductor island;

forming a first gate electrode over the first semiconductor island with the gate insulating layer interposed therebetween; and

forming a second gate electrode over the second semiconductor island with the gate insulating layer interposed therebetween,

wherein the first semiconductor island is formed in a peripheral circuit portion, and

wherein the second semiconductor island is formed in a display portion.

11. The method for manufacturing the display device according to claim 10,

wherein the step of forming the first gate electrode, comprises the step of forming a lower gate electrode and an upper gate electrode over the lower gate electrode.

12. The method for manufacturing the display device according to claim 11, further comprising the steps of:

forming a first impurity region and a second impurity region,

wherein a concentration of an impurity in the first impurity region is larger than that of the second impurity region,

wherein the first impurity region does not overlap with the upper gate electrode and the lower gate electrode, and

wherein the second impurity region overlaps the lower gate electrode, and does not overlap the upper gate electrode.

13. The method for manufacturing the display device according to claim 10,

wherein the step of forming the bonding layer, comprises the step of:

forming a first bonding layer comprising at least one of silicon nitride, silicon nitride oxide, and silicon oxynitride; and

forming a second bonding layer over the first bonding layer, comprising one of silicon oxide containing hydrogen and silicon nitride containing hydrogen, or silicon nitride containing oxygen and hydrogen, silicon oxynitride containing oxygen and hydrogen, and silicon nitride oxide containing oxygen and hydrogen.

14. The method for manufacturing the display device according to claim 10, further comprising the steps of:

forming an interlayer insulating film over the second gate electrode and the first gate electrode;

forming an contact hole in the interlayer insulating film; and

forming a pixel electrode over the interlayer insulating film, so as to connect the second semiconductor island via the contact hole.

15. A method for manufacturing a display device comprising the steps of:

doping an ion into a region in a first substrate, wherein the first substrate is a single crystal semiconductor substrate;

forming a bonding layer over the first substrate;

adhering the bonding layer to a second substrate, wherein the second substrate has an insulating surface;

forming a semiconductor layer over the second substrate with the bonding layer interposed therebetween, by cleaving the first substrate using the region as a cleavage plane;

forming a first semiconductor island and a second semiconductor island, by etching the semiconductor layer;

forming a first gate insulating layer over the first semiconductor island and over the second semiconductor island;

forming a first gate electrode over the first semiconductor island with the first gate insulating layer interposed therebetween;

forming a second gate insulating layer over the first gate electrode and the first gate insulating layer;

forming a second gate electrode over the second semiconductor island with the first gate insulating layer and the second gate insulating layer interposed therebetween,

wherein the first semiconductor island is formed in a peripheral circuit portion, and

wherein the second semiconductor island is formed in a display portion.

16. The method for manufacturing the display device according to claim 15,

wherein the step of forming the first gate electrode, comprises the step of forming a lower gate electrode and an upper gate electrode over the lower gate electrode.

17. The method for manufacturing the display device according to claim 16, further comprising the steps of:

forming a first impurity region and a second impurity region,

wherein a concentration of an impurity in the first impurity region is larger than that of the second impurity region,

wherein the first impurity region does not overlap with the upper gate electrode and the lower gate electrode, and

wherein the second impurity region overlaps the lower gate electrode, and does not overlap the upper gate electrode.

18. The method for manufacturing the display device according to claim 15,

wherein the step of forming the bonding layer, comprises the step of:

forming a first bonding layer comprising at least one of silicon nitride, silicon nitride oxide, and silicon oxynitride; and

forming a second bonding layer over the first bonding layer, comprising one of silicon oxide containing hydrogen and silicon nitride containing hydrogen, or silicon nitride containing oxygen and hydrogen, silicon oxynitride containing oxygen and hydrogen, and silicon nitride oxide containing oxygen and hydrogen.

19. The method for manufacturing the display device according to claim 15, further comprising the steps of:

forming an interlayer insulating film over the second gate electrode and the first gate electrode;

forming an contact hole in the interlayer insulating film; and

forming a pixel electrode over the interlayer insulating film, so as to connect the second semiconductor island via the contact hole.