CONDUCTIVE LINE COMPRISING A CAPPING LAYER

• US 20090140307A1
• Filed: 11/29/2007
• Published: 06/04/2009
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Eifler, Andreas, Tegen, Stefan, Muemmler, Klaus, Baars, Peter
• Granted Patent: US 7,777,266 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/488 Word lines

Abstract

An integrated circuit includes a conductive line, the conductive line having a conductive layer made of a metal or a first compound including a metal and a capping layer made of a second compound comprising the metal, the capping layer being in contact with the conductive layer, the first compound being different from the second compound.

Claims

1. A method of forming an integrated circuit, comprising:

forming a groove in a supporting material;

forming a liner layer in the groove;

forming a first compound comprising a metal over the liner layer in the groove;

removing a portion of the liner layer and the first metal compound corresponding to an upper portion of the groove, wherein the liner layer and the first metal compound remain in a lower portion of the groove; and

forming a capping layer over the first metal compound in the groove, wherein the capping layer comprises a second compound of the metal, the second compound being different than the first metal compound.

2. The method of claim 1, further comprising removing the capping layer, thereby exposing the first metal compound in the lower portion of the trench.

3. The method of claim 1, wherein the supporting material comprises a semiconductor body, the method further comprising forming an insulating layer in the groove before forming the liner layer, wherein the liner layer is conductive.

4. The method of claim 1, further comprising forming a sacrificial layer on sidewalls of the upper portion of the groove and over the first metal compound prior to forming the capping layer over the first metal compound.

5. The method of claim 4, wherein the sacrificial layer comprises a silicon layer, and wherein forming the capping layer comprises performing a thermal process, thereby causing a portion of the first metal compound to react with the silicon layer thereover to form the second metal compound.

6. The method of claim 1, further comprising:

bringing the first compound into contact with a sacrificial material; and

reacting the first compound with the sacrificial material.

7. The method of claim 1, further comprising removing any residue on sidewalls of the groove in the upper portion thereof, wherein the first metal compound is protected by the second metal compound during the residue removal.

8. An integrated circuit comprising a conductive line, comprising:

an intermediate layer comprising a first metal in contact with a dielectric layer;

a conductive layer comprising a first compound comprising a second metal in contact with the intermediate layer; and

a capping layer comprising a second compound comprising the second metal in contact with the conductive layer, wherein the first compound is different than the second compound.

9. The integrated circuit of claim 8, further comprising a groove in a supporting material, wherein the intermediate layer, the conductive layer, and the capping layer reside in the groove.

10. The integrated circuit of claim 9, wherein the supporting material comprises a semiconductor body, further comprising a dielectric layer in the groove residing between the semiconductor body and the intermediate layer.

11. The integrated circuit of claim 10, further comprising a transistor comprising source/drain regions in the semiconductor body on at least one side of the groove, wherein the dielectric layer comprises a gate dielectric layer, wherein the intermediate layer and the conductive layer comprise a gate electrode, and wherein the groove defines a channel in the semiconductor body between the opposing source/drain regions, and wherein the channel comprises vertical and horizontal components.

12. The integrated circuit of claim 11, wherein the intermediate layer comprises titanium nitride, and the conductive layer comprises tungsten.

13. The integrated circuit of claim 11, wherein the transistor comprises an access transistor in a DRAM memory array, wherein a conductive wordline couples to the gate electrode residing in the groove.

14. The integrated circuit of claim 13, wherein the conductive wordline comprises a buried wordline residing in the groove, wherein the groove extends longitudinally in a wordline direction and couples to a plurality of different gate electrodes of different access transistors of different DRAM memory cells along the wordline direction, wherein the different access transistors along the wordline direction have source/drain regions isolated from one another.

15. An integrated circuit, formed by the process of:

forming a groove in a supporting material comprising a semiconductor body;

forming a dielectric layer in the groove;

forming a liner layer over the dielectric layer in the groove;

forming a first metal compound over the liner layer in the groove;

removing a portion of the liner layer and the first metal compound corresponding to an upper portion of the groove, wherein the liner layer and the first metal compound remain in a lower portion of the groove;

forming a capping layer over the first metal compound in the groove, wherein the capping layer comprises a second metal compound that is different than the first metal compound; and

removing any residue on sidewalls of the groove in the upper portion thereof, wherein the first metal compound is protected by the second metal compound during the residue removal.

16. The integrated circuit of claim 15, further formed by the process of removing the capping layer, thereby exposing the first metal compound in the lower portion of the trench.

17. The integrated circuit of claim 15, further comprising a sacrificial layer formed by the process of forming a sacrificial layer on sidewalls of the upper portion of the groove and over the first metal compound prior to forming the capping layer over the first metal compound.

18. The integrated circuit of claim 17, wherein the sacrificial layer comprises a silicon layer, and wherein the capping layer is formed by the process of performing a thermal process, thereby causing a portion of the first metal compound to react with the silicon layer thereover to form the second metal compound.

19. The integrated circuit of claim 15, further comprising source/drain regions formed by the process of forming source/drain regions in the semiconductor body on opposing sides of the groove, thereby forming a transistor and defining a channel therebetween in the semiconductor body along the groove, wherein the channel comprises vertical and horizontal components.

20. The integrated circuit of claim 19, wherein the intermediate layer comprises titanium nitride, and the conductive layer comprises tungsten.

21. The integrated circuit of claim 19, wherein the transistor comprises an access transistor in a DRAM memory array, wherein a conductive wordline couples to the gate electrode residing in the groove.

22. The integrated circuit of claim 19, wherein the conductive wordline comprises a buried wordline residing in the groove, wherein the groove extends longitudinally in a wordline direction and couples to a plurality of different gate electrodes of different access transistors of different DRAM memory cells along the wordline direction, wherein the different access transistors along the wordline direction have source/drain regions isolated from one another.