Nonvolatile memory devices and methods of forming the same

• US 20090140313A1
• Filed: 11/25/2008
• Published: 06/04/2009
• Est. Priority Date: 11/30/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Joo, Joon-Yong
• Application Number:
  US12/292,732
• Publication Number:
  US 20090140313A1
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of forming nonvolatile memory devices according to example embodiments of the present invention includes forming a device isolation layer defining active regions in a semiconductor substrate; forming a plurality of transistors on the active regions, the plurality of transistors comprising a pair of adjacent string selection transistors, a pair of adjacent ground selection transistors, and a plurality of memory cell transistors connected in series between the string selection transistors and ground selection transistors; forming a common source line using SEG between a pair of adjacent ground selection transistors so that the common source line has a top surface lower than a top surface of the pair of adjacent ground selection transistors.

Claims

1. A method of forming a nonvolatile memory device, comprising:

forming a device isolation layer defining active regions in a semiconductor substrate;

forming a plurality of transistors on the active regions, the plurality of transistors comprising a pair of adjacent string selection transistors, a pair of adjacent ground selection transistors, and a plurality of memory cell transistors connected in series between the string selection transistors and ground selection transistors;

forming a common source line using selective epitaxial growth (SEG) between a pair of adjacent ground selection transistors so that the common source line has a top surface lower than a top surface of the pair of adjacent ground selection transistors.

2. The method of claim 1, wherein forming the common source line includes further forming a metal silicide layer on a silicon layer formed using SEG.

3. The method of claim 1, wherein the common source lines are epitaxially grown so that the common source lines extend onto the device isolation layer from the active regions and are connected to each other.

4. The method of claim 3, wherein forming the common source line comprises:

forming a spacer insulating layer on gate structures of the transistors;

forming a common source trench by etching the spacer insulating layer so as to selectively expose the active regions and the device isolation layer which are related to the common source line; and

forming a silicon layer on the active regions exposed by the common source trench using SEG.

5. The method of claim 4, further comprising:

anisotropically etching the spacer insulating layer to form a sidewall spacer on a sidewall of the gate structure.

6. The method of claim 5, further comprising:

forming an insulating interlayer on the semiconductor substrate including sidewall spacers;

forming contact holes exposing the active regions between a pair of adjacent string selection transistors; and

forming bit lines on the insulating interlayer, the bit lines being connected to the active regions between a pair of adjacent string selection transistors by contact plugs which fill the contact holes.

7. The method of claim 1, wherein the active regions extend in a specific direction and are formed to be parallel to each other, and wherein the device isolation layer additionally defines a common source region connecting the active regions by extending in a direction crossing the active regions so as to correspond to the common source line.

8. The method of claim 7, wherein the common source region is doped in the same manner as the source/drain regions of the adjacent ground selection transistor.

9. The method of claim 7, wherein forming the common source line comprises:

forming gate structures of the transistors on the semiconductor substrate;

forming sidewall spacers on sidewalls of the gate structures, the sidewall spacers exposing the active regions between a pair of adjacent ground selection transistors and a pair of adjacent string selection transistors; and

forming a silicon layer on the exposed active regions and the common source active region using SEG.

10. The method of claim 9, wherein the sidewall spacers additionally expose the active regions between the selection transistors and the memory cell transistors most adjacent to the selection transistors.

11. The method of claim 9, wherein the silicon layers are separated from each other on a top surface of the device isolation layer.

12. The method of claim 11, further comprising selectively forming metal silicide layers on the silicon layers formed using SEG.

13. The method of claim 11, wherein forming the gate structure comprises forming a tunnel oxide layer on the active region, a charge storage layer, a blocking insulating layer, a polysilicon layer and a capping layer, and wherein the method further comprises:

exposing the polysilicon layer by selectively removing the capping layer exposed by the sidewall spacers after an epitaxial growth of the silicon layers; and

selectively forming a metal silicide layer on the silicon layers formed using SEG and on the polysilicon layer.

14. The method of claim 13, wherein the capping layer has an etch selectivity with respect to the sidewall spacers, the silicon layer and the polysilicon layer.

15. A nonvolatile memory device, comprising:

a device isolation layer defining active regions in a semiconductor substrate;

a pair of adjacent string selection transistors on the active regions;

a pair of adjacent ground selection transistors on the active regions;

a plurality of memory cell transistors connected in series between the string selection transistors and the ground selection transistors on the active region; and

a common source line including a first silicon layer and a first metal silicide layer on the first silicon layer formed on the active region between the pair of adjacent ground selection transistors using selective epitaxial growth (SEG), wherein the common source line has a top surface lower than top surfaces of the transistors.

16. The nonvolatile memory device of claim 15, wherein the first silicon layers of the common source lines extend onto the device isolation layer and are connected to each other, the first silicon layers having an epitaxial structure on the device isolation layer.

17. The nonvolatile memory device of claim 15, wherein the active regions extend in a specific direction and are parallel to each other, the common source regions extending in a direction crossing the active regions to connect the active regions.

18. The nonvolatile memory device of claim 17, further comprising:

sidewall spacers disposed on sidewalls of the gate structures of the transistors, the sidewall spacers exposing active regions between the pair of adjacent ground selection transistors and between the pair of adjacent string selection transistors; and

a second silicon layer and a second metal silicide layer on the second silicon layer formed on the active region between the pair of adjacent string selection transistors and the common source region using SEG.

19. The nonvolatile memory device of claim 18, further comprising a third silicon layer and a third metal silicide on the third silicon layer formed on the active regions between the selection transistors and the memory cell transistors most adjacent to the selection transistors using SEG.

20. The nonvolatile memory device of claim 18, wherein the gate structure comprises a tunnel oxide layer on the active region, a charge storage layer, a blocking insulating layer, a polysilicon layer and a fourth metal silicide layer, and wherein the first and second metal silicide layers have the same metal as the fourth metal silicide layer.