SHORT GATE HIGH POWER MOSFET AND METHOD OF MANUFACTURE

• US 20090140326A1
• Filed: 12/03/2007
• Published: 06/04/2009
• Est. Priority Date: 12/03/2007
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Harris, Christopher, Konstantinov, Andrei, Svederg, Jan-Olov
• Granted Patent: US 8,084,813 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A short gate high power metal oxide semiconductor field effect transistor formed in a trench includes a short gate having gate length defined by spacers within the trench. The transistor further includes a buried region that extends beneath the trench and beyond a corner of the trench, that effectively shields the gate from high drain voltage, to prevent short channel effects and resultantly improve device performance and reliability.

Claims

1. A semiconductor device comprising:

a substrate of a first conductivity type;

a region of a second conductivity type within the substrate, the region extending from an upper surface of the substrate into the substrate, the second conductivity type opposite the first conductivity type;

a first layer of the first conductivity type over the substrate and the region;

a trench extending into the first layer, a bottom of the trench is within the first layer and a portion of the first layer is intermediate between the bottom of the trench and the region;

a gate having gate sections over the portion of the first layer at the bottom of the trench and covering sidewalls of the trench, a central area of the portion of the first layer at the bottom of the trench exposed between the gate sections;

an insulating layer covering an upper surface of the first layer and the gate sections, and within the trench covering the central area of the portion of the first layer at the bottom of the trench; and

a source contact overlying the insulating layer, the source contact extending through the insulating layer and the central area of the portion of the first layer at the bottom of the trench, to contact the central area of the portion of the first layer at the bottom of the trench and the region.

2. The semiconductor device of claim 1, wherein the substrate and the first layer are silicon carbide epitaxial layers.

3. The semiconductor device of claim 1, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

4. The semiconductor device of claim 1, wherein the region is an implanted region.

5. The semiconductor device of claim 1, wherein the gate is polysilicon.

6. The semiconductor device of claim 1, having a gate length in a range of about 0.3 to 1.5 μ

m.

7. The semiconductor device of claim 1, wherein the region has a dopant concentration that is graded in the vertical direction.

8. The semiconductor device of claim 1, further comprising:

a plurality of additional regions of the second conductivity type within the substrate, the plurality of additional regions extending from the upper surface of the substrate into the substrate,

a plurality of additional trenches extending into the first layer and having respective trench bottoms within the first layer, respective portions of the first layer intermediate between the trench bottoms and the additional regions; and

a plurality of additional gates each having gate sections over the respective portions of the first layer at the trench bottoms and covering sidewalls of the additional trenches, central areas of the respective portions of the first layer at the trench bottoms exposed between the gate sections of the additional gates,

wherein the source contact and the insulating layer overlie an entirety of the semiconductor device, and

wherein the source contact extends through the insulating layer and the central areas of the respective portions of the first layer at the trench bottoms to be in contact with the central areas of the respective portions of the first layer at the trench bottoms and the additional regions.

9. A vertical field effect transistor comprising:

a first layer of a first conductivity type;

an implanted region of a second conductivity type extending into the first layer, the second conductivity type opposite the first conductivity type;

a second layer of the first conductivity type on an upper surface of the first layer and an upper surface of the implanted region;

a trench extending into the second layer above the implanted region, a portion of the second layer is disposed intermediate between a bottom of the trench and the implanted regions the implanted region extending laterally beyond sidewalls of the trench;

a gate having gate sections within the trench and covering the sidewalls of the trench, a central area of the portion of the second layer at the bottom of the trench is exposed between the gate sections;

an insulating layer covering the second layer and the gate sections, and within the trench;

a source contact overlying the insulating layer, the source contact extending through the insulating layer within the trench and the central area of the portion of the second layer at the bottom of the trench, to contact the implanted region and the second layer; and

a drain contact on a bottom surface of the first layer, the bottom surface on a side of the first layer opposite the upper surface.

10. The vertical field effect transistor of claim 9, wherein the first and second layers are silicon carbide epitaxial layers.

11. The vertical field effect transistor of claim 9, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

12. The vertical field effect transistor of claim 9, wherein the gate is polysilicon.

13. The vertical field effect transistor of claim 9, wherein the implanted region has a dopant concentration that is graded in the vertical direction.

14. The vertical field effect transistor of claim 9, having a gate length in a range of about 0.3 to 1.5 μ

m.

15. A method of manufacturing a semiconductor device comprising:

forming a first region in a substrate of a first conductivity type, the first region extending from an upper surface of the substrate into the substrate and having a second conductivity type that is opposite the first conductivity type;

forming a first layer of the first conductivity type over the substrate and the first region;

forming a trench extending into the first layer, a bottom of the trench is within the first layer and a portion of the first layer is intermediate between the bottom of the trench and the first region;

forming a gate having gate sections over the portion of the first layer at the bottom of the trench and covering sidewalls of the trench, a central area of the portion of the first layer at the bottom of the trench is exposed between the gate sections;

forming an insulating layer covering an upper surface of the first layer and the gate sections, and within the trench covering the central area of the portion of the first layer at the bottom of the trench; and

forming a source contact overlying the insulating layer, the source contact extending through the insulating layer and the central area of the portion of the first layer at the bottom of the trench, to contact the central area of the portion of the first layer at the bottom of the trench and the first region.

16. The method of manufacturing a semiconductor device of claim 15, wherein said forming a gate comprises:

depositing a gate layer over an entirety of the first layer and within the trench; and

etching the gate layer to remove the gate layer from over the first layer, so that only portions of the gate layer remain covering the sidewalls of the trench as the gate sections.

17. The method of manufacturing a semiconductor device of claim 16, wherein the gate is polysilicon.

18. The method of manufacturing a semiconductor device of claim 15, further comprising forming a source contact area of relatively high dopant concentration in the portion of the first layer at the bottom of the trench prior to said forming a gate, by implanting an impurity having the first conductivity type.

19. The method of manufacturing a semiconductor device of claim 15, wherein the first conductivity type is n-type and the second conductivity type is p-type.

20. The method of manufacturing a semiconductor device of claim 15, wherein the substrate and the first layer are epitaxially grown silicon carbide layers.

21. The method of manufacturing a semiconductor device of claim 15, wherein a dopant concentration of the first region is graded in a vertical direction.

22. The method of manufacturing a semiconductor device of claim 15, wherein gate length of the semiconductor device is in a range of about 0.3 to 1.5 μ

m.

23. A method of manufacturing a vertical field effect transistor comprising:

providing a first layer of a first conductivity type;

implanting a first region of a second conductivity type in the first layer, the second conductivity type being opposite the first conductivity type;

forming a second layer of the first conductivity type on an upper surface of the first layer and an upper surface of the implanted region;

forming a trench extending into the second layer above the implanted region, a portion of the second layer is disposed intermediate between a bottom of the trench and the first region, the first region extending laterally beyond sidewalls of the trench;

forming a gate having gate sections within the trench and covering the sidewalls of the trench, a central area of the portion of the second layer at the bottom of the trench is exposed between the gate sections;

forming an insulating layer covering the second layer and the gate sections, and within the trench;

forming a source contact overlying the insulating layer, the source contact extending through the insulating layer within the trench and through the central area of the portion of the second layer at the bottom of the trench, to contact the implanted region and the second layer; and

forming a drain contact on a bottom surface of the first layer, the bottom surface on a side of the first layer opposite the upper surface.

24. The method of manufacturing a vertical field effect transistor of claim 23, wherein said forming a gate comprises:

depositing a gate layer over an entirety of the second layer and within the trench; and

etching the gate layer to remove the gate layer from over the second layer, so that only portions of the gate layer remain covering the sidewalls of the trench as the gate sections.

25. The method of manufacturing a vertical field effect transistor of claim 24, wherein the gate is polysilicon.

26. The method of manufacturing a vertical field effect transistor of claim 23, further comprising forming a source contact area of relatively high dopant concentration in the portion of the second layer at the bottom of the trench prior to said forming a gate, by implanting an impurity having the first conductivity type.

27. The method of manufacturing a vertical field effect transistor of claim 23, wherein the first conductivity type is n-type and the second conductivity type is p-type.

28. The method of manufacturing a vertical field effect transistor of claim 23, wherein the first and second layers are epitaxially grown silicon carbide layers.

29. The method of manufacturing a vertical field effect transistor of claim 23, wherein a dopant concentration of the first region is graded in a vertical direction.

30. The method of manufacturing a vertical field effect transistor of claim 23, wherein a gate length of the vertical field effect transistor is in a range of about 0.3 to 1.5 μ

m.