LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH A TRENCH FIELD PLATE

• US 20090140343A1
• Filed: 12/04/2007
• Published: 06/04/2009
• Est. Priority Date: 12/04/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Zierak, Michael J., Voldman, Steven H., Feilchenfeld, Natalie B., Gambino, Jeffrey P., Voegeli, Benjamin T., Lanzerotti, Louis D.
• Granted Patent: US 7,956,412 B2
• Time in Patent Office: Days
• US Class Current: 257/367
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A dielectric material layer is formed on a bottom surface and sidewalls of a trench in a semiconductor substrate. The silicon oxide layer forms a drift region dielectric on which a field plate is formed. Shallow trench isolation may be formed prior to formation of the drift region dielectric, or may be formed utilizing the same processing steps as the formation of the drift region dielectric. A gate dielectric layer is formed on exposed semiconductor surfaces and a gate conductor layer is formed on the gate dielectric layer and the drift region dielectric. The field plate may be electrically tied to the gate electrode, may be an independent electrode having an external bias, or may be a floating electrode. The field plate biases the drift region to enhance performance and extend allowable operating voltage of a lateral diffusion field effect transistor during operation.

Claims

1. A semiconductor structure comprising:

a trench located in a semiconductor substrate and containing at least one trench sidewall and a trench bottom surface;

a body having a doping of a first conductivity type and located in said semiconductor substrate;

a drift region having a doping of a second conductivity type and bounded by said at least one trench sidewall and said trench bottom surface, wherein said second conductivity type is the opposite of said first conductivity type;

a drift region dielectric of unitary construction comprising a dielectric material, located directly on and inside of said trench, and containing a bottom dielectric portion vertically abutting said trench bottom surface and a sidewall dielectric portion laterally abutting said at least one trench sidewall; and

a gate electrode abutting said gate dielectric and said bottom dielectric portion.

2. The semiconductor structure of claim 1, further comprising:

a source region having a doping of said second conductivity type, located in said semiconductor substrate, abutting said body, and disjoined from said drift region; and

a drain region having a doping of said second conductivity type, located in said semiconductor substrate, abutting said drift region, and disjoined from said body.

3. The semiconductor structure of claim 2, further comprising a gate spacer laterally abutting said gate electrode, wherein said source region is self-aligned to an edge of said gate electrode with an offset and said drain region is self-aligned to one of said at least one trench sidewall.

4. The semiconductor structure of claim 1, wherein said at least one trench sidewall extends from a top surface of said semiconductor substrate to a depth into said semiconductor substrate and said trench bottom surface is located at said depth and adjoins said at least one trench sidewall, and wherein the entirety of said trench bottom surface and said at least one trench sidewall directly contacts said drift region dielectric, and wherein a top surface of said bottom dielectric portion is recessed from said top surface of said semiconductor substrate.

5. The semiconductor structure of claim 1, wherein said silicon oxide comprises thermal silicon oxide.

6. A semiconductor structure comprising:

a trench located in a semiconductor substrate and containing at least one trench sidewall and a trench bottom surface;

a body having a doping of a first conductivity type and located in said semiconductor substrate;

a drift region having a doping of a second conductivity type and bounded by said at least one sidewall and said trench bottom surface, wherein said second conductivity type is the opposite of said first conductivity type;

a drift region dielectric of unitary construction comprising a dielectric material, located directly on and inside of said trench, and containing a bottom dielectric portion vertically abutting said trench bottom surface and a sidewall dielectric portion laterally abutting said at least one trench sidewall;

a gate electrode abutting said gate dielectric; and

a field plate located within said trench, vertically abutting said bottom dielectric portion, and disjoined from said gate electrode.

7. The semiconductor structure of claim 6, further comprising a field plate cap comprising a dielectric material and abutting said gate electrode and said field plate.

8. The semiconductor structure of claim 7, wherein a top surface of said field plate cap is substantially coplanar with a top surface of said semiconductor substrate.

9. The semiconductor structure of claim 6, further comprising a contact via vertically abutting said field plate and electrically isolated from said gate electrode.

10. The semiconductor structure of claim 6, wherein said field plate is electrically floating and is capacitively coupled to said gate electrode.

11. The semiconductor structure of claim 6, further comprising:

a source region having a doping of said second conductivity type, located in said semiconductor substrate, abutting said body, and disjoined from said drift region; and

a drain region having a doping of said second conductivity type, located in said semiconductor substrate, abutting said drift region, and disjoined from said body.

12. A method of forming a semiconductor structure comprising:

forming a trench having at least one trench sidewall and a trench bottom surface in a semiconductor substrate;

forming a drift region dielectric of unitary construction comprising a dielectric material and containing a bottom dielectric portion vertically abutting said trench bottom surface and a sidewall dielectric portion laterally abutting said at least one trench sidewall;

forming a body having a doping of a first conductivity type and disjoined from said trench in said semiconductor substrate;

forming a drift region having a doping a second conductivity type, abutting said at least one trench sidewall and said trench bottom surface, and laterally abutting said body at an interface extending to a top surface of said semiconductor substrate;

forming a gate dielectric on said body and said drift region, wherein said gate dielectric directly contacts said drift region dielectric; and

forming a gate electrode abutting said gate dielectric and said bottom dielectric portion.

13. The method of claim 12, further comprising:

forming a gate spacer laterally abutting said gate electrode;

forming a source region having a doping of said second conductivity type in said semiconductor substrate, wherein said source region abuts said body and is disjoined from said drift region and is self-aligned to an edge of said gate electrode with an offset; and

forming a drain region having a doping of said second conductivity type in said semiconductor substrate, wherein said drain region abuts said drift region and disjoined from said body and is self-aligned to one of said at least one trench sidewall.

14. The method of claim 12, wherein said dielectric material comprises thermal silicon oxide.

15. The method of claim 12, further comprising:

forming another trench in said semiconductor substrate at the same processing step as said forming of said trench;

forming shallow trench isolation comprising another dielectric material in said trench and said another trench; and

removing said another dielectric material in said trench to expose said trench bottom surface and said at least one trench sidewall, while preserving said another dielectric material in said another trench prior to said forming of said drift region dielectric.

16. A method of forming a semiconductor structure comprising:

forming a trench having at least one trench sidewall and a trench bottom surface in a semiconductor substrate;

forming a drift region dielectric of unitary construction comprising a dielectric material and containing a bottom dielectric portion vertically abutting said trench bottom surface and a sidewall dielectric portion laterally abutting said at least one trench sidewall;

depositing a conductive material directly on said bottom dielectric portion and recessing said conductive material beneath a top surface of said semiconductor substrate to form a field plate;

forming a body having a doping of a first conductivity type and disjoined from said trench in said semiconductor substrate;

forming a drift region having a doping a second conductivity type, abutting said at least one trench sidewall and said trench bottom surface, and laterally abutting said body at an interface extending to a top surface of said semiconductor substrate;

forming a gate dielectric on said body and said drift region, wherein said gate dielectric directly contacts said drift region dielectric; and

forming a gate electrode abutting said gate dielectric and said bottom dielectric portion.

17. The method of claim 16, further comprising forming a field plate cap comprising another dielectric material directly on said field plate, wherein said field plate cap abuts said gate electrode after formation of said gate electrode.

18. The method of claim 17, further comprising:

forming another trench in said semiconductor substrate at the same processing step as said forming of said trench;

depositing said dielectric material in said another trench at the same processing step as said forming of said drift region dielectric;

depositing said another dielectric material in said another trench after said recessing of said conductive material to form shallow trench isolation; and

planarizing said another dielectric material over said trench to form said field plate cap.

19. The method of claim 17, further comprising:

forming another trench in said semiconductor substrate at the same processing step as said forming of said trench;

depositing said dielectric material in said another trench at the same processing step as said forming of said drift region dielectric;

depositing said another dielectric material in said another trench to form shallow trench isolation; and

planarizing said conductive material over said trench prior to said recessing of said conductive material, wherein said conductive material is a doped silicon containing material and said field plate cap comprises thermal silicon oxide.

20. The method of claim 16, further comprising:

forming a gate spacer laterally abutting said gate electrode;

forming a source region having a doping of said second conductivity type in said semiconductor substrate, wherein said source region abuts said body and is disjoined from said drift region and is self-aligned to an edge of said gate electrode with an offset; and

forming a drain region having a doping of said second conductivity type in said semiconductor substrate, wherein said drain region abuts said drift region and disjoined from said body and is self-aligned to one of said at least one trench sidewall.