METHOD AND A SEMICONDUCTOR DEVICE COMPRISING A PROTECTION LAYER FOR REDUCING STRESS RELAXATION IN A DUAL STRESS LINER APPROACH

• US 20090140348A1
• Filed: 06/02/2008
• Published: 06/04/2009
• Est. Priority Date: 11/30/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Werner, Thomas, Griebenow, Uwe, Frohberg, Kai, Feustel, Frank
• Granted Patent: US 8,105,962 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

By providing a protection layer for suppressing stress relaxation in a tensile-stressed dielectric material during a dual stress liner approach, performance of N-channel transistors may be increased, while nevertheless maintaining a high degree of compatibility with conventional dual stress liner approaches.

Claims

1. A method, comprising:

forming a first stress-inducing dielectric layer above a P-channel transistor and an N-channel transistor;

selectively removing a portion of said first stress-inducing layer from above said P-channel transistor;

forming a second stress-inducing dielectric layer above said P-channel transistor and said N-channel transistor;

selectively removing a portion of said second stress-inducing layer from above said N-channel transistor;

forming a dielectric buffer layer above said first and second stress-inducing dielectric layers by a non-plasma assisted deposition process; and

depositing an interlayer dielectric material by performing a plasma enhanced chemical vapor deposition process.

2. The method of claim 1, wherein said first stress-inducing layer is a tensile-stressed layer and is formed prior to forming said second stress-inducing layer.

3. The method of claim 2, further comprising forming an etch stop layer above said P-channel transistor and said N-channel transistor prior to forming said first stress-inducing layer.

4. The method of claim 3, further comprising forming an etch control layer on said first stress-inducing layer prior to forming said second stress-inducing layer.

5. The method of claim 4, wherein selectively removing said portion of the second stress-inducing layer comprises performing an etch process and using said etch control layer to determine an endpoint of said etch process.

6. The method of claim 2, wherein said dielectric buffer layer is formed prior to selectively removing said portion of said first stress-inducing layer from above said P-channel transistor.

7. The method of claim 6, further comprising forming an etch control layer on said dielectric buffer layer and using said etch control layer for controlling an etch process so as to selectively remove said second stress-inducing layer from above said N-channel transistor, while maintaining at least a portion of an initial layer thickness of said dielectric buffer layer.

8. The method of claim 1, wherein performing said non-plasma assisted deposition process comprises performing a thermally activated chemical vapor deposition process.

9. The method of claim 8, wherein said thermally activated chemical vapor deposition process is performed on the basis of TEOS (tetra ethyl orthosilicate) to deposit silicon dioxide.

10. The method of claim 1, wherein performing said non-plasma assisted deposition process comprises applying said dielectric buffer layer by spin coating.

11. The method of claim 1, wherein said second stress-inducing layer is formed prior to forming said first stress-inducing layer.

12. The method of claim 11, wherein said second stress-inducing layer is selectively removed from said N-channel transistor prior to forming said first stress-inducing layer.

13. The method of claim 12, wherein said dielectric buffer layer is formed prior to selectively removing said portion of said first stress-inducing layer.

14. The method of claim 12, wherein said dielectric buffer layer is formed after selectively removing said portion of said first stress-inducing layer.

15. The method of claim 13, wherein said non-plasma assisted deposition process is performed as a thermally activated chemical vapor deposition process.

16. A method, comprising:

forming a tensile-stressed dielectric layer above an N-channel transistor;

forming a dielectric buffer material on said tensile-stressed dielectric layer by performing a deposition process without using a plasma ambient; and

depositing an interlayer dielectric material above said dielectric buffer material by using a plasma assisted deposition process.

17. The method of claim 16, wherein said dielectric buffer material is deposited by performing a thermally activated chemical vapor deposition process.

18. The method of claim 16, wherein said dielectric buffer material is deposited by performing a spin coating process.

19. The method of claim 18, further comprising forming a contact opening in said interlayer dielectric material using said dielectric buffer material as a first etch stop material.

20. A semiconductor device, comprising:

a first transistor formed above a substrate;

a second transistor formed above said substrate;

a first stress-inducing dielectric layer formed above said first transistor and inducing a first type of strain in a channel region of said first transistor;

a second stress-inducing dielectric layer formed above said second transistor and inducing a second type of strain in a channel region of said second transistor;

a polymer material formed above said first and second stress-inducing layers; and

a silicon dioxide based interlayer dielectric material formed above said polymer material.

21. The semiconductor device of claim 20, wherein said first transistor is an N-channel transistor and said first stress-inducing layer is a tensile-stressed layer.

22. The semiconductor device of claim 21, wherein said second transistor is a P-channel transistor and said second stress-inducing layer is compressive layer.