Semiconductor Device and Method of Making Integrated Passive Devices

• US 20090140421A1
• Filed: 12/03/2007
• Published: 06/04/2009
• Est. Priority Date: 10/29/2005
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Zhang, Qing, Chen, Kang, Fang, Jianmin, Lin, Yaojian, Cao, Haijing
• Granted Patent: US 8,409,970 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization.

Claims

1. A method of making a semiconductor device, comprising:

providing a first substrate on a backside of the semiconductor device;

forming a first insulating layer over the first substrate;

forming a first conductive layer over the first insulating layer;

forming a second insulating layer over the first conductive layer;

forming a second conductive layer over the second insulating layer;

forming a third conductive layer over the first insulating layer;

forming a first passivation layer over the first, second, and third conductive layers;

forming a fourth conductive layer over the first passivation layer in electrical contact with the third conductive layer;

forming a second passivation layer over the first passivation layer;

attaching a carrier to the second passivation layer;

removing the first substrate;

forming a non-silicon substrate over the first insulating layer on the backside of the semiconductor device; and

removing the carrier.

2. The method of claim 1, wherein the non-silicon substrate is made with a material selected from the group consisting of glass, molding compound, epoxy, polymer, and polymer composite.

3. The method of claim 1, wherein the fourth conductive layer is coiled on the first passivation layer to have an inductive property.

4. The method of claim 1, wherein the first and second conductive layers and the second insulating layer have a capacitive property.

5. The method of claim 1, further including forming a via between the first insulating layer and first passivation layer.

6. The method of claim 1, further including:

forming an under bump metallization over the second passivation layer; and

forming a solder bump on the under bump metallization.

7. The method of claim 1, further including forming a resistive layer over the first insulating layer.

8. A method of making a semiconductor device, comprising:

providing a first substrate on a backside of the semiconductor device;

forming a first insulating layer over the first substrate;

forming a first conductive layer over the first insulating layer;

forming a first passivation layer over the first conductive layer;

forming a second conductive layer over the first passivation layer in electrical contact with the first conductive layer;

forming a second passivation layer over the first passivation layer;

attaching a carrier to the second passivation layer;

removing the first substrate;

forming a non-silicon substrate over the first insulating layer on the backside of the semiconductor device; and

removing the carrier.

9. The method of claim 8, wherein the non-silicon substrate is made with a material selected from the group consisting of glass, molding compound, epoxy, polymer, and polymer composite.

10. The method of claim 8, further including:

forming a third conductive layer over the first insulating layer;

forming a second insulating layer over the third conductive layer; and

forming a fourth conductive layer over the second insulating layer.

11. The method of claim 10, wherein the third and fourth conductive layers and the second insulating layer have a capacitive property.

12. The method of claim 8, wherein the second conductive layer is coiled on the first passivation layer to have an inductive property.

13. The method of claim 8, further including forming a via between the first insulating layer and first passivation layer.

14. The method of claim 8, further including:

forming an under bump metallization over the second passivation layer; and

forming a solder bump on the under bump metallization.

15. The method of claim 8, further including forming a resistive layer over the first insulating layer.

16. A method of making a semiconductor device, comprising:

providing a first substrate on a backside of the semiconductor device;

forming an insulating layer over the first substrate;

forming a passive circuit element over the insulating layer;

forming a passivation layer over the passive circuit element;

attaching a carrier to the passivation layer;

removing the first substrate;

forming a non-silicon substrate over the first insulating layer on the backside of the semiconductor device; and

removing the carrier.

17. The method of claim 16, wherein the non-silicon substrate is made with a material selected from the group consisting of glass, molding compound, epoxy, polymer, and polymer composite.

18. The method of claim 16, further including forming an adhesive layer between the non-silicon substrate and first insulating layer.

19. The method of claim 16, further including forming a via between the insulating layer and first passivation layer.

20. The method of claim 16, wherein the passive circuit element is an inductor, capacitor, or resistor.

21. The method of claim 16, further including:

forming an under bump metallization over the passivation layer in electrical contact with the passive circuit element; and

forming a solder bump on the under bump metallization.

22. A semiconductor device, comprising:

a non-silicon substrate;

an insulating layer formed over the non-silicon substrate;

a passive circuit element formed over the first insulating layer;

a passivation layer formed over the passive circuit element;

an under bump metallization formed over the passivation layer in electrical contact with the passive circuit element; and

a solder bump formed on the under bump metallization.

23. The semiconductor device of claim 22, further including an adhesive layer formed between the non-silicon substrate and insulating layer.

24. The semiconductor device of claim 22, further including a via formed between the insulating layer and passivation layer.

25. The semiconductor device of claim 22, wherein the passive circuit element is an inductor, capacitor, or resistor.