SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20090140438A1
• Filed: 12/01/2008
• Published: 06/04/2009
• Est. Priority Date: 12/03/2007
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KUWABARA, Hideaki, YAMAZAKI, Shunpei
• Application Number:
  US12/325,474
• Publication Number:
  US 20090140438A1
• Time in Patent Office: Days
• US Class Current: 257/776
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Wirings each having a side face with a different angle, which is made accurately, in a desired portion over one mother glass substrate are provided without increasing the steps. With the use of a multi-tone mask, a photoresist layer is formed, which has a tapered shape in which the area of a cross section is reduced gradually in a direction away from one mother glass substrate. At the time of forming one wiring, one photomask is used and a metal film is selectively etched, whereby one wiring having a side face, the shape (specifically, an angle with respect to a principal plane of a substrate) of which is different depending on a place, is obtained.

Claims

1. A semiconductor device comprising:

a semiconductor layer over a substrate; and

a wiring partially overlapping with the semiconductor layer,

wherein the wiring includes a region where the width of a wiring side portion is large and a region where the width of a wiring side portion is small, and

wherein the region where the width of a wiring side portion is large overlaps with at least part of the semiconductor layer, and an angle of the side face in a cross section in a wiring width direction is smaller than that of the region where the width of a wiring side portion is small by greater than or equal to 10°

.

2. The semiconductor device according to claim 1, wherein the angle of the side face in a cross section in a wiring width direction of the region where the width of a wiring side portion is large is in the range of 10°

to 50°

.

3. The semiconductor device according to claim 1, wherein the angle of the side face in a cross section in a wiring width direction of the region where the width of a wiring side portion is small is in the range of 60°

to 90°

.

4. The semiconductor device according to claim 1, wherein the region where a wiring side portion is narrow does not overlap with the semiconductor layer.

5. A semiconductor device comprising:

a first wiring over a substrate;

an insulating film covering the first wiring; and

a second wiring electrically connected to the first wiring with <

through>

the insulating film interposed therebetween,

wherein, between two end portions of the second wiring in the cross-sectional shape, an angle of one side face with respect to a principal plane of the substrate is different from an angle of the other side face with respect to the principal plane of the substrate.

6. A semiconductor device according to claim 5, further comprising:

a transparent conductive film partially overlapping with the second wiring,

wherein, between two end portions of the second wiring in the cross-sectional shape, one side face where an angle with respect to the principal plane of the substrate is small is in contact with the transparent conductive film.

7. A semiconductor device comprising:

a first wiring and a second wiring having a cross-sectional shape different from that of the first wiring over the same insulating film surface,

wherein, a cross-sectional shape of the first wiring is a rectangle or a trapezoid,

wherein, the cross-sectional shape of the second wiring has a stair step in which one side face has two or more steps, and

wherein, the first wiring and the second wiring are formed of the same material.

8. A method for manufacturing a semiconductor device comprising the steps of:

forming a conductive layer over a substrate;

performing light exposure once using a multi-tone mask and developing a first resist mask and a second resist mask which are different in an angle between a side face in a cross section and a principal plane of the substrate; and

forming wirings by etching the conductive layer using the first resist mask and the second resist mask as masks,

wherein, after the development, a difference between an angle on the side face of the first resist mask and an angle on the side face of the second resist mask is greater than 10°

.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the cross-sectional shape of the first resist mask is a rectangle or a trapezoid, and the cross-sectional shape of the second resist mask is a trapezoid.

10. The method for manufacturing a semiconductor device according to claim 8,