High Performance Variable Gain Amplifier, Method of Use and Design Structure

• US 20090140809A1
• Filed: 12/03/2007
• Published: 06/04/2009
• Est. Priority Date: 12/03/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chi, Howard H.
• Granted Patent: US 7,688,142 B2
• Time in Patent Office: Days
• US Class Current: 330/254
• CPC Class Codes: H03F 2203/45052 the cascode stage of the cascode differential amplifier being controlled by a controlling signal, which controlling signal can also be the input signal
• CPC Class Codes: H03F 2203/45302 the common gate stage of a cascode dif amp being controlled
• CPC Class Codes: H03F 2203/45318 the AAC comprising a cross coupling circuit, e.g. two extra transistors cross coupled
• CPC Class Codes: H03F 2203/45366 the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45392 the AAC comprising resistors in the source circuit of the AAC before the common source coupling
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 3/45089 Non-folded cascode stages
• CPC Class Codes: H03G 1/0023 in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence

Abstract

A circuit of high performance variable gain amplifier, method of use and design structure on which the subject circuit resides is provided. The circuit comprises a plurality of differential stages having a common input, and output, a common control level input CM and respective individual control level inputs C_x. The circuit also includes a fixed stage that always is biased to an “on” state from the common input.

Claims

1. A circuit, comprising:

a plurality of differential stages having a common input, a common control level input CM and respective individual control level inputs C_x; and

a fixed stage that always is biased to an “

on”

state from the common input.

2. The circuit of claim 1, wherein the common control level input CM and the respective individual control level inputs C_x establish cross points.

3. The circuit of claim 1, wherein the plurality of differential stages have fixed tail currents.

4. The circuit of claim 1, wherein outputs of the plurality of differential stages are in parallel.

5. The circuit of claim 1, wherein inputs to each of the plurality of differential stages from the common input are in parallel.

6. The circuit of claim 1, wherein the common control level input CM is configured to steer current away from transistors under control of the respective individual control level inputs C_x as a voltage of the common control level input CM incrementally increases above a voltage for each of the individual control level inputs C_x.

7. The circuit of claim 1 is a high linear and low noise figure circuit having a dynamic range beyond 10 dB.

8. The circuit of claim 7, wherein the dynamic range is about 33 dB.

9. The circuit of claim 1 is a high linear and low noise figure circuit that exhibits approximately 5 dB NF (noise figure) at high gain.

10. The circuit of claim 1 is a high linear and low noise figure circuit with about a 10 dB power gain requiring less than 10 mA at about 3.3V supply.

11. The circuit of claim 1, wherein the plurality of differential stages is four stages.

12. The circuit of claim 1, wherein a voltage of the common control level input CM is between about 2.6 volts (low) to about 2.8 volts (high).

13. The circuit of claim 1, wherein the respective individual control level inputs C_x have an equal voltage difference “

delta”

therebetween.

14. A method, comprising:

setting cross points;

choosing a gain and maximizing linearity by setting degeneration resistor values and DC bias currents for each stage, and load resistors RL; and

creating multi-stage switching cores.

15. The method of claim 14, selecting a number of stages of the multistage core by determining at least one of total current available and linearity at a particular gain point or within a gain range.

16. The method of claim 14, wherein the setting cross points is provided at voltage intersections of common control level input CM and respective individual control level inputs C_x of a plurality of differential stages.

17. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a plurality of differential stages having a common input and output, a common control level input CM and a respective individual control level input C_x; and

a fixed stage that always is biased to an “

on”

state from the common input.

18. The design structure of claim 17, wherein the design structure comprises a netlist.

19. The design structure of claim 17, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.