Semiconductor Devices and Methods of Manufacture Thereof

• US 20090141424A1
• Filed: 11/29/2007
• Published: 06/04/2009
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Ruderer, Erwin, Kaltalioglu, Erdem, Barth, Hans-Joachim, Baumgartner, Peter, Riess, Philipp, Tews, Helmut Horst, Benetik, Thomas, Glasow, Alexander Von
• Granted Patent: US 8,138,539 B2
• Time in Patent Office: Days
• US Class Current: 361/311
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

Claims

1. A capacitor plate, comprising:

a plurality of first parallel conductive members;

a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members;

a first base member coupled to an end of the plurality of first parallel conductive members;

a second base member coupled to an end of the plurality of second parallel conductive members; and

a connecting member disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member comprises at least one elongated via.

2. The capacitor plate according to claim 1, wherein the connecting member comprises at least one elongated via comprising a width and a length, wherein the length is greater than the width.

3. The capacitor plate according to claim 2, wherein the connecting member comprises a plurality of elongated vias disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, the plurality of elongated vias being spaced apart by a distance substantially the same as the width of the elongated vias.

4. The capacitor plate according to claim 1, wherein the connecting member comprises a single elongated via disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, the single elongated vias comprising a first length, wherein the plurality of second parallel connecting members comprise a second length, and wherein the second length is substantially the same as the first length.

5. The capacitor plate according to claim 4, wherein the connecting member further comprises a third base member disposed between the first base member and the second base member.

6. A capacitor, comprising:

a first plate;

a second plate; and

an insulating material disposed between the first plate and the second plate, wherein the first plate and the second plate each comprise;

a plurality of first parallel conductive members;

a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members;

a first base member coupled to an end of at least some of the plurality of first parallel conductive members;

a second base member coupled to an end of at least some of the plurality of second parallel conductive members; and

a connecting member disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member comprises at least one elongated via.

7. The capacitor according to claim 6, wherein the connecting member comprises a first connecting member, wherein the first plate and the second plate each further comprise a plurality of third parallel conductive members disposed over the plurality of second parallel conductive members, and a second connecting member disposed between the plurality of third parallel conductive members and the second parallel conductive members, wherein the second connecting member comprises at least one elongated via.

8. The capacitor according to claim 6, wherein the connecting member comprises at least one elongated via comprising a width and a length, wherein the length is about twice or greater than the width.

9. The capacitor according to claim 6, wherein the connecting member comprises at least a top portion comprising substantially the same length and width as a portion of the plurality of second parallel conductive members.

10. The capacitor according to claim 6, wherein the plurality of first parallel conductive members of the first plate are interwoven with the plurality of first parallel conductive members of the second plate, and wherein the plurality of second parallel conductive members of the first plate are interwoven with the plurality of second parallel conductive members of the second plate.

11. A semiconductor device, comprising:

a workpiece;

a plurality of first parallel conductive members disposed over the workpiece, the plurality of first parallel conductive members having a first end and a second end;

a connecting member disposed over and coupled at least to the plurality of first parallel conductive members, the connecting members comprising at least one elongated via;

a plurality of second parallel conductive members disposed over and coupled to the connecting members, the plurality of second parallel conductive members having a first end and a second end;

a first base member coupled to the first end of every other of the plurality of first parallel conductive members, the first base member electrically coupling an alternating plurality of first parallel conductive members together;

a second base member coupled to the second end of the plurality of first parallel conductive members not connected to the first base member, the second base member electrically coupling an alternating plurality of first parallel conductive members together;

a third base member coupled to the first end of every other of the plurality of second parallel conductive members, the third base member electrically coupling an alternating plurality of second parallel conductive members together; and

a fourth base member coupled to the second end of the plurality of second parallel conductive members not connected to the third base member, the fourth base member electrically coupling an alternating plurality of second parallel conductive members together.

12. The semiconductor device according to claim 11, wherein the plurality of first parallel conductive members coupled to the first base member and the plurality of second parallel conductive members coupled to the third base member comprise a portion of a first capacitor plate, and wherein the plurality of first parallel conductive members coupled to the second base member and the plurality of second parallel conductive members coupled to the fourth base member comprise a portion of a second capacitor plate.

13. The semiconductor device according to claim 11, further comprising an insulating material disposed at least between the plurality of first parallel conductive members, the plurality of second parallel conductive members, and the connecting members.

14. The semiconductor device according to claim 11, wherein the connecting members comprise first connecting members, further comprising a second connecting member disposed between the first base member and the third base member or between the second base member and the fourth base member, and wherein the second connecting member comprises at least one elongated via or at least one minimum feature sized via.

15. The semiconductor device according to claim 11, wherein the plurality of first parallel conductive members are disposed within a first metallization layer of the semiconductor device, wherein the connecting members are disposed within a second metallization layer of the semiconductor device, wherein the plurality of second parallel conductive members are disposed within a third metallization layer of the semiconductor device, wherein the first and third metallization layers comprise conductive line layers of the semiconductor device, and wherein the second metallization layer comprises a via layer of the semiconductor device.

16. A method of manufacturing a capacitor, the method comprising:

providing a workpiece;

forming a first plate and a second plate over the workpiece; and

forming a capacitor dielectric between the first plate and the second plate, wherein forming the first plate and the second plate each comprise;

forming a plurality of first parallel conductive members;

forming a plurality of second parallel conductive members over the plurality of first parallel conductive members;

coupling a first base member to an end of at least some of the plurality of first parallel conductive members;

coupling a second base member to an end of at least some of the plurality of second parallel conductive members; and

forming a connecting member between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein forming the connecting member comprises forming at least one elongated via, and wherein forming the first plate and the second plate comprises interweaving the plurality of first parallel conductive members of the first plate with the plurality of first parallel conductive members of the second plate, and interweaving the plurality of second parallel conductive members of the first plate with the plurality of second parallel conductive members of the second plate.

17. The method according to claim 16, wherein forming the connecting member comprises forming an insulating material, patterning the insulating material, forming a liner over the insulating material, and forming a fill material over the liner;

and wherein forming the liner comprises forming a liner with continuous coverage.

18. The method according to claim 16, wherein the plurality of first parallel conductive members and the first base members are formed in a first insulating material, wherein forming the connecting members comprises forming a second insulating material having a lower portion and an upper portion over the first insulating material and patterning at least the lower portion of the second insulating material using a first lithography mask, wherein forming the second parallel conductive members and the second base members comprise patterning the upper portion of the second insulating material using a second lithography mask, before or after patterning the at least the lower portion of the second insulating material with the first lithography mask, further comprising filling the patterns in the second insulating material with a conductive material.

19. The method according to claim 16, wherein the plurality of first parallel conductive members and the first base members are formed in a first insulating material, wherein forming the connecting members and the second parallel conductive members comprises forming a second insulating material having a lower portion and an upper portion over the first insulating material and patterning the lower portion and the upper portion of the second insulating material using a first lithography mask, wherein forming the second base members comprises patterning the upper portion of the second insulating material using a second lithography mask, before or after patterning the lower portion and the upper portion of the second insulating material with the first lithography mask, further comprising filling the patterns in the second insulating material with a conductive material.

20. The method according to claim 16, wherein the plurality of first parallel conductive members and the first base member are formed in a first insulating material, wherein forming the connecting members, the second parallel conductive members, and the second base members comprise forming a second insulating material over the first insulating material and patterning the second insulating material using a single lithography mask, further comprising filling the patterns in the second insulating material with a conductive material.

21. The method according to claim 16, wherein forming the first plate and the second plate each comprise:

not coupling at least one of the first parallel conductive members to the first base member, or not coupling at least one of the second parallel conductive members to the second base member.

22. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece;

forming a first conductive material layer over the workpiece, the first conductive material layer including a first insulating material and a plurality of first parallel conductive members disposed within the first insulating material;

forming a via layer over the first conductive material layer, the via layer including a second insulating material and a connecting member coupled to the first parallel conductive members, the connecting members being disposed within the second insulating material and comprising at least one elongated via; and

forming a second conductive material layer over the via layer, the second conductive material layer including a third insulating material and a plurality of second parallel conductive members disposed within the third insulating material, the plurality of second parallel conductive members being coupled to a connecting member, wherein the plurality of first parallel conductive members, the plurality of second parallel conductive members, and the connecting members comprise at least one capacitor plate.

23. The method according to claim 22, wherein forming the first conductive material layer, forming the via layer, or forming the second conductive material layer comprises a single damascene process, a dual damascene process, or a subtractive etch process.

24. The method according to claim 22, wherein providing the workpiece comprises providing a workpiece comprising a capacitor region and a conductive line region, wherein the method comprises forming the plurality of first parallel conductive members, the connecting members, and the plurality of second parallel conductive members in the capacitor region, further comprising forming a plurality of vias in the conductive line region when forming the via layer, the plurality of vias comprising a minimum feature size of the semiconductor device.

25. The method according to claim 24, wherein forming the via layer comprises depositing the second insulating material, providing a lithography mask, using the lithography mask to pattern the second insulating material, and filling the patterned second insulating material with a conductive material, wherein the patterns of the lithography mask comprise a greater width and smaller length in the conductive line region than in the capacitor region.