Method of operating a phase-change memory device

• US 20090141546A1
• Filed: 04/16/2008
• Published: 06/04/2009
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Khang, Yoon-ho, Kim, Cheol-kyu, Kim, Ki-joon
• Granted Patent: US 8,116,125 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells

Abstract

A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.

Claims

1. A method of operating a phase-change memory device having a phase-change layer, and a unit applying a voltage to the phase-change layer, the method comprising:

applying a reset voltage to the phase-change layer,

wherein the reset voltage includes at least two pulse voltages which are continuously applied.

2. The method of claim 1, wherein the at least two pulse voltages are applied with identical magnitude.

3. The method of claim 2, wherein the at least two pulse voltages are substantially equal.

4. The method of claim 1, wherein a pulse width of each of the at least two pulse voltages is less than 20 ns.

5. The method of claim 4, wherein the pulse width of each of the at least two pulse voltages ranges from 5 ns to 20 ns.

6. The method of claim 4, wherein an interval of 100 ns or less is between each of the at least two pulse voltages.

7. The method of claim 6, wherein the interval between the at least two pulse voltages ranges from 5 ns to 100 ns.

8. The method of claim 4, wherein an interval greater than 5 ns is between each of the at least two pulse voltages.

9. The method of claim 8, wherein the interval is less than 100 ns.

10. The method of claim 1, wherein an interval of 100 ns or less is between each of the at least two pulse voltages.

11. The method of claim 10, wherein the interval between the at least two pulse voltages ranges from 5 ns to 100 ns.

12. The method of claim 1, wherein an interval greater than 5 ns is between each of the at least two pulse voltages.

13. The method of claim 12, wherein the interval is less than 100 ns.

14. The method of claim 1, wherein a number of the pulse voltages applied ranges 2 to 10.

15. The method of claim 1, further comprising applying a set voltage to the phase-change layer, after the reset voltage is applied.

16. The method of claim 15, wherein the reset voltage is applied for an equal or shorter amount of time than the set voltage.