Semiconductor device having memory array, method of writing, and systems associated therewith

• US 20090141567A1
• Filed: 11/07/2008
• Published: 06/04/2009
• Est. Priority Date: 11/09/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Beak Hyung, Lee, Kwang Jin, Wang, Qi
• Granted Patent: US 8,223,527 B2
• Time in Patent Office: Days
• US Class Current: 365/189.150
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.

Claims

1. A semiconductor device, comprising:

a non-volatile memory cell array;

a control unit configured to generate a mode signal indicating if a flash mode has been enabled;

a write circuit configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.

2. The semiconductor device of claim 1, wherein the control unit is configured to generate the mode signal based on input signals.

3. The semiconductor device of claim 1, wherein

the control unit is configured to generate an erase enable signal indicating whether an erase operation is enabled, the control unit is configured to generate an erase enable signal indicating the erase operation is not enabled if the mode signal indicating that the flash mode has not been enabled;

and wherein

the write circuit is configured to write in the non-volatile memory cell array based on the mode signal and the erase enable signal.

4. The semiconductor device of claim 3, wherein the control unit is configured to generate the erase enable signal based on an input command and the mode signal.

5. The semiconductor device of claim 3, further comprising:

an input buffer configured to output to the write circuit one of input data and erase data based on the erase enable signal.

6. The semiconductor device of claim 5, wherein the write circuit comprises:

a selector configured to selectively output one of a fixed enable signal and an inverse of the input data as a write enable signal based on the mode signal and the erase enable signal; and

a write driver configured to write the output from the input buffer in the non-volatile memory cell array if enabled by the write enable signal, the fixed enable signal enabling the write driver if output as the write enable signal.

7. The semiconductor device of claim 6, wherein

the selector is configured to output the fixed enable signal if the flash mode is enabled and the erase operation is enabled;

the selector is configured to output the fixed enable signal if the flash mode is not enabled; and

the selector is configured to output the inverse of the input data if the flash mode is enabled and the erase operation is not enabled.

8. The semiconductor device of claim 7, further comprising:

an address buffer configured to generate at least one address based on at least one of an input address and the erase enable signal.

9. The semiconductor device of claim 8, wherein the address buffer generates a plurality of addresses if the erase operation is enabled.

10. The semiconductor device of claim 1, wherein the mode control circuit is configured to change the mode signal.

11. The semiconductor device of claim 1, wherein

the non-volatile memory cell array is divided into a plurality of memory portions;

and

the control unit includes,

a mode memory configured to store a flag associated with each memory portion indicating whether the flash mode applies to the memory portion;

a mode control unit configured to access a flag in the mode memory based on an input address, and configured to generate the mode signal based on the accessed flag.

12. The semiconductor device of claim 1, further comprising:

a read circuit configured to read data from the non-volatile memory cell array; and

wherein

the control unit is configured to control the read circuit to read data associated with an address input for a write operation during pre-read operation; and

the write circuit is configured to disable writing data in memory locations of the non-volatile memory cell array storing data matching the write data during the pre-read operation based on the read data.

13. The semiconductor device of claim 12, wherein

the control unit is configured to generate a pre-read enable signal indicating whether the pre-read operation is enabled;

and

the write circuit is configured to disable the write operation if the read data matches data associated with the write operation and the pre-read enable signal indicates the pre-read operation is enabled.

14. The semiconductor device of claim 13, wherein the control unit is configured to generate the pre-read enable signal based on input signals.

15. The semiconductor device of claim 13, wherein the write circuit comprises:

a write driver configured to write data;

a comparator comparing the write data to the read data; and

at least one selector selectively supplying output of the comparator to the write driver as an enable signal based on the pre-read enable signal.

16. The semiconductor device of claim 1, further comprising:

a read circuit configured to read data from the non-volatile memory cell array; and

wherein

the control unit is configured to control the read circuit to read data associated with an address input for a write operation during pre-read operation; and

the write circuit is configured to write logic ‘

1’

only in the addresses of the non-volatile memory cell array for which a logic ‘

0’

was read during pre-read operation during an erase operation if the flash mode is enabled.

19. The method of claim 1, further comprising:

disabling writing data in memory locations of the non-volatile memory cell array storing data matching the write data during a pre-read operation.

17. A semiconductor device, comprising:

a non-volatile memory cell array including a first portion and a second portion;

a mode control circuit configured to generate a first mode signal indicating if a flash mode has been enabled for the first portion of the non-volatile memory cell array, and the mode control circuit configured to generate a second mode signal indicating if a flash mode has been enabled for the second portion of the non-volatile memory cell array;

a first write circuit configured to write in the first portion of the non-volatile memory cell array based on the first mode signal such that the first write circuit disables erasing the first portion of the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the first portion of the non-volatile memory cell array is received; and

a second write circuit configured to write in the second portion of the non-volatile memory cell array based on the second mode signal such that the second write circuit disables erasing the second portion of the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the second portion of the non-volatile memory cell array is received.

18. A method of writing to a non-volatile memory cell array, comprising:

disabling erasing the non-volatile memory cell array if a flash mode of operation has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array are received.

20. A card, comprising:

a memory, the memory including,

a non-volatile memory cell array;

a control unit configured to generate a mode signal indicating if a flash mode has been enabled;

a write circuit configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received; and

a control unit configured to control the memory.

21. A system, comprising:

a bus;

a semiconductor device connected to the bus, the semiconductor device including,

a non-volatile memory cell array;

a control unit configured to generate a mode signal indicating if a flash mode has been enabled;

a write circuit configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received; and

an input/output device connected to the bus; and

a processor connected to the bus, the processor configured to communicate with the input/output device and the semiconductor device via the bus.