FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION

• US 20090142897A1
• Filed: 12/23/2008
• Published: 06/04/2009
• Est. Priority Date: 02/23/2005
• Status: Active Grant

• Current Assignee: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz, Robert S. Chau, Suman Datta
• Original Assignee: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz, Robert S. Chau, Suman Datta
• Inventors: Chau, Robert S., Doczy, Mark L., Kavalieros, Jack, Brask, Justin K., Datta, Suman, Metz, Matthew
• Granted Patent: US 7,825,481 B2
• Time in Patent Office: Days
• US Class Current: 438/285
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te

Abstract

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Claims

1. A method of forming a transistor comprising:

forming a gate electrode on a gate dielectric layer formed on a silicon layer; and

forming a pair of source/drain regions on opposite sides of said gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film.

2. The method of claim 1 wherein said narrow bandgap semiconductor film is selected from the group consisting of indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (In_1-xGa_xAs (x>

50%)) and indium phosphide (InP).

3. The method of claim 1 wherein said narrow bandgap semiconductor has a energy bandgap of less than 0.75 eV.

4. A method of forming a transistor comprising:

forming a gate dielectric layer on a first surface of a silicon layer;

forming a gate electrode on said gate dielectric layer, said gate electrode having a pair of laterally opposite sidewalls;

forming a pair of sidewall spacers adjacent to said sidewalls of said gate electrode;

etching a pair of recesses into said silicon layer adjacent to said outside edges of said sidewall spacers and beneath said gate electrode formed on said gate dielectric layer; and

depositing a narrow bandgap semiconductor film in said recesses.

5. The method of claim 4 wherein said narrow bandgap semiconductor has an energy bandgap of less than 0.75 eV.

6. The method of claim 4 wherein said narrow bandgap semiconductor film is deposited at a temperature less than 550°

C.

7. The method of claim 4 wherein said narrow bandgap semiconductor film is deposited in said recesses until said narrow bandgap semiconductor film extends above said first surface.

8. The method of claim 4 wherein said narrow bandgap semiconductor film is doped to an n type conductivity while depositing said narrow bandgap semiconductor film.

9. The method of claim 4 wherein said low bandgap semiconductor film is doped to a p type conductivity while depositing said low bandgap semiconductor film.

10. The method of claim 4 further comprises a step of forming a non-alloy contact onto said low bandgap semiconductor film.

11. The method of claim 10 further comprising forming a contact comprising titanium/gold in direct contact with said low bandgap semiconductor film.

12. The method of claim 4 wherein said recesses are etched with a wet etchant comprising an ammonium hydroxide or asyemmtric or symmetric tetra (alkyl) ammonium hydroxides (alkyl=methyl, ethyl, propyl, isopropyl, butyl, tert-butyl;

symmetric meaning all 4 alkyl groups are the same.

13. The method of claim 4 wherein said narrow bandgap semiconductor film is a selectively grown epitaxial film.

14. The method of claim 13 wherein said narrow bandgap semiconductor is indium antimonide (InSb) grown by a MOCVD process utilizing an equimolar gaseous mixture of volatized trimethylindium and stibane (SbH₃) with about 5% each by mass in a carrier gas such as argon.