SYSTEMS AND METHODS FOR SAMPLE RATE CONVERSION

• US 20090143884A1
• Filed: 12/23/2008
• Published: 06/04/2009
• Est. Priority Date: 03/21/2003
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Andersen, Jack B., Hand, Larry E., Chieng, Daniel L.W.
• Granted Patent: US 7,970,088 B2
• Time in Patent Office: Days
• US Class Current: 700/94
• CPC Class Codes: H03F 2200/03 the amplifier being designed for audio applications
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03H 17/0275 comprising non-recursive filters
• CPC Class Codes: H03H 17/0642 the ratio being arbitrary or irrational
• CPC Class Codes: H03H 17/0685 the ratio being rational

Abstract

Systems and methods are provided for converting input data streams having variable input sample rates to an output sample rate, which systems and methods are used in processing the data streams. In one embodiment, a system includes a clock source, a counter configured to count cycles for a corresponding data stream, and a data processor. The data processor is configured to read the number of cycles counted by the counter between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted.

Claims

1. A system, comprising:

a counter to count cycles of a clock signal in a sample period corresponding to a digital data stream by incrementing once for each clock cycle after a frame sync signal is received in the digital data stream; and

a data processor to convert the digital data stream from an input sample rate to a predetermined output sample rate based on the number of cycles counted in the digital data stream.

2. The system of claim 1, wherein the input sample rate is not predetermined.

3. The system of claim 1, wherein the data processor resets the counter each time a succeeding frame sync signal is received.

4. The system of claim 1, wherein the system is implemented in a sample rate converter.

5. The system of claim 1, further comprising:

a buffer to store data from the digital data stream while the data processor converts the digital data stream to the predetermined output sample rate.

6. The system of claim 5, wherein the buffer comprises a first in first out (FIFO) buffer.

7. A method comprising:

receiving a clock signal and a digital data stream;

counting a number of cycles of the clock signal in a sample period corresponding to the digital data stream by incrementing once for each clock cycle after a frame sync signal is received in the digital data stream; and

converting the digital data stream from an input sample rate to a predetermined output sample rate based on the number of cycles counted in the digital data stream.

8. The method of claim 7, wherein the input sample rate is not predetermined.

9. The method of claim 7, further comprising:

resetting the counting each time a succeeding frame sync signal is received.

10. The method of claim 7, further comprising:

storing data from the digital data stream while converting the digital data stream to the predetermined output sample rate.

11. The method of claim 7, wherein the method is implemented in a sample rate converter.

12. The method of claim 7, wherein the method is implemented in a pulse-width modulated digital audio amplifier.

13. A digital audio amplification system, comprising:

an audio signal path including at least

a sample rate converter (SRC),

an audio effects subsystem,

a pulse width modulation (PWM) modulator, and

an output stage;

wherein SRC receives a digital data stream having an input sample rate, and outputs a digital data stream having a predetermined output sample rate based on a number of cycles counted in the received digital data stream between successive frame sync signals.

14. A digital audio amplification system of claim 13, wherein the input sample rate is not predetermined.

15. The digital audio amplification system of claim 13, wherein the SRC comprises:

a counter to count cycles of a clock signal in a sample period corresponding to the digital data stream by incrementing once for each clock cycle after a frame sync signal is received in the digital data stream; and

a data processor to convert the digital data stream from a non-predetermined input sample rate to a predetermined output sample rate based on the number of cycles counted in the digital data stream;

wherein the counter is reset each time a succeeding frame sync signal is received.

16. The digital audio amplification system of claim 15, wherein the SRC further comprises:

a buffer to store data from the digital data stream while the data processor converts the digital data stream to the predetermined output sample rate.

17. The digital audio amplification system of claim 16, wherein the buffer comprises a first in first out (FIFO) buffer.

18. A sample rate converter, comprising:

an input to receive a digital data stream having an input sample rate; and

means for converting the digital data stream from the input sample rate to a predetermined output sample rate based on a number of cycles counted in the received digital data stream between successive frame sync signals.

19. The sample rate converter of claim 18, wherein the means for converting comprises:

a counter to count cycles of a clock signal in a sample period corresponding to the digital data stream by incrementing once for each clock cycle after a frame sync signal is received in the digital data stream; and

a data processor to convert the digital data stream from the input sample rate to the predetermined output sample rate based on the number of cycles counted in the digital data stream;

wherein the counter is reset each time a succeeding frame sync signal is received.

20. The sample rate converter of claim 18, wherein the input sample rate is not predetermined.