Enhanced Microprocessor or Microcontroller
First Claim
1. A microprocessor or microcontroller device comprising:
- a central processing unit (CPU);
a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks; and
a plurality of special function registers and general purpose registers which may be memory-mapped to said data memory, wherein at least the following special function registers are memory-mapped to all memory banks;
a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and
wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from said context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.
15 Assignments
0 Petitions
Accused Products
Abstract
A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.
19 Citations
18 Claims
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1. A microprocessor or microcontroller device comprising:
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a central processing unit (CPU); a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks; and a plurality of special function registers and general purpose registers which may be memory-mapped to said data memory, wherein at least the following special function registers are memory-mapped to all memory banks;
a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; andwherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from said context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of operating a microprocessor or microcontroller device comprising a central processing unit (CPU);
- a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks;
a plurality of special function registers and general purpose registers, the method comprising the steps of;memory mapping at least the following special function registers to all memory banks;
a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch;upon occurrence of a context switch, saving automatically the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from said context switch restoring the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
- a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks;
Specification