Enhanced Microprocessor or Microcontroller
First Claim
1. An n-bit microprocessor device comprising:
- an n-bit central processing unit (CPU);
a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, comprising at least two 16-bit indirect memory address registers which are accessible by said CPU across all banks;
a bank access unit for coupling said CPU with one of said plurality of banks;
a data memory coupled with the CPU; and
a program memory coupled with the CPU,wherein said indirect address registers are operable to access said data memory or program memory and wherein a bit in each of said indirect memory address registers indicates an access to said data memory or to said program memory.
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Accused Products
Abstract
An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are accessible by the CPU across all banks; a bank access unit for coupling the CPU with one of the plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein the indirect address registers are operable to access the data memory or program memory and wherein a bit in each of the indirect memory address registers indicates an access to the data memory or to the program memory.
16 Citations
20 Claims
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1. An n-bit microprocessor device comprising:
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an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, comprising at least two 16-bit indirect memory address registers which are accessible by said CPU across all banks; a bank access unit for coupling said CPU with one of said plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein said indirect address registers are operable to access said data memory or program memory and wherein a bit in each of said indirect memory address registers indicates an access to said data memory or to said program memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for operating an n-bit microprocessor device comprising the steps of:
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providing an n-bit central processing unit (CPU); providing a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, providing at least two 16-bit indirect memory address registers which are accessible by said CPU across all banks; providing a bank access unit for coupling said CPU with one of said plurality of banks; providing a data memory coupled with the CPU; providing a program memory coupled with the CPU; and performing an indirect addressing using an indirect address register to access said data memory or program memory, wherein a bit in each of said indirect memory address registers indicates an access to said data memory or to said program memory, respectively. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification