STREAM PROCESSING APPARATUS, METHOD FOR STREAM PROCESSING AND DATA PROCESSING SYSTEM

• US 20090144527A1
• Filed: 11/28/2008
• Published: 06/04/2009
• Est. Priority Date: 11/29/2007
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: IZUHARA, Fumitaka, AKIE, Kazushi, KIMURA, Motoki, YUASA, Takafumi, NAKATA, Hiroaki
• Application Number:
  US12/324,951
• Publication Number:
  US 20090144527A1
• Time in Patent Office: Days
• US Class Current: 712/221
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

The present invention provides a stream processing apparatus capable of improving the processing performance in the case of continuously processing a plurality of data streams. A control stream, different from a data stream, is prepared, and a program and a parameter are updated in advance in accordance with the control stream. Double buffer areas are prepared in a memory of the stream processing apparatus into which the program and the parameter are stored. The location of the data stream to be input is written in the control stream, and buffers for reading the data stream are multiplexed so as to read in advance the top portion of the data stream to be processed next.

Claims

1. A stream processing apparatus which inputs a data stream to perform an arithmetic process and outputs the result as a data stream, the stream processing apparatus comprising:

a buffer memory; and

a processor,

wherein information necessary for a stream process is input to the buffer memory as a control stream, the control stream contains information on where to obtain the data stream to be input and a parameter necessary for the arithmetic process of the data stream, the data stream is input to the buffer memory in accordance with the information on where to obtain the data stream, and the processor performs the arithmetic process for the data stream input to the buffer memory on the basis of the parameter of the control stream.

2. The stream processing apparatus according to claim 1, comprising a register which specifies a location where the control stream is stored.

3. The stream processing apparatus according to claim 1, comprising a transfer control apparatus which transfers the control stream and the data stream to the buffer memory from the outside of the stream processing apparatus.

4. The stream processing apparatus according to claim 3, comprising a control unit which analyzes the control stream to obtain the parameter and the information on where to obtain the data stream, and sets transfer control conditions to the transfer control apparatus.

5. The stream processing apparatus according to claim 4, comprising a data memory to which the parameter is transferred and which is accessible by the processor.

6. The stream processing apparatus according to claim 5,

wherein the control unit obtains information on an arithmetic procedure from the control stream, the stream processing apparatus includes an instruction memory to which the obtained information on the arithmetic procedure is transferred and which is accessible by the processor, and the processor performs the arithmetic process using the information on the arithmetic procedure read from the instruction memory.

7. The stream processing apparatus according to claim 5,

wherein the control stream contains information on starting of a sub-control stream, the sub-control stream contains a parameter necessary for a process of the data stream, the control unit sets the transfer control conditions to the transfer control unit in accordance with the content of the control stream so as to transfer the sub-control stream to the buffer memory, and the processor performs the arithmetic process on the basis of the parameter of the sub-control stream transferred to the buffer.

8. The stream processing apparatus according to claim 6,

wherein the control stream contains information on starting of a sub-control stream, the sub-control stream contains the information on the arithmetic procedure necessary for a process of the data stream, the control unit sets the transfer control conditions to the transfer control unit in accordance with the content of the sub-control stream so as to transfer the sub-control stream to the buffer memory, and the processor performs the arithmetic process on the basis of the information of the arithmetic procedure transferred to the buffer.

9. The stream processing apparatus according to claim 1,

wherein in a process of one input data stream, the result is output while being divided into a plurality of data streams.

10. The stream processing apparatus according to claim 1, referring to a plurality of input streams, performing the arithmetic process by referring to the input streams, and outputting the result of the arithmetic process.

11. The stream processing apparatus according to claim 1,

wherein the processor performs a stream process in accordance with the arithmetic procedure, the buffer memory temporarily stores the input data stream and the data stream to be output, and the processor can randomly access the buffer memory.

12. The stream processing apparatus according to claim 1,

wherein the processor performs a stream process in accordance with the arithmetic procedure, the stream processing apparatus includes a data memory for storing data to be written or read by the processor, the data memory can perform an address conversion process when being accessed from the processor, and the address conversion is a process in which when a process of one data stream is completed and a process of the next data stream is started, logical addresses mapped to a memory area where one data stream is stored and a memory area where the other data stream is stored are switched to each other.

13. The stream processing apparatus according to claim 1,

wherein the processor performs a stream process in accordance with the arithmetic procedure, the stream processing apparatus includes an instruction memory for storing a program showing the arithmetic procedure of the processor, the instruction memory can perform an address conversion process when being accessed from the processor, and the address conversion is a process in which when a process of one data stream is completed and a process of the next data stream is started, logical addresses mapped to a memory area where the program showing the arithmetic procedure for one data stream is stored and a memory area where the program showing the arithmetic procedure for the next data stream is stored are switched to each other.

14. A stream processing apparatus which inputs a data stream to perform an arithmetic process and outputs the result as a data stream, the stream processing apparatus comprising:

a buffer memory;

a data transfer control apparatus which is used for data transfer control between the buffer memory and the outside of the stream processing apparatus; and

a processor which is used for an arithmetic process of the data stream stored in the buffer memory,

wherein the data transfer control apparatus transfers the data stream to the buffer memory on the basis of information on where to obtain the data stream held by a control stream stored in the buffer memory, and the processor performs the arithmetic process for the data stream in the buffer memory on the basis of a parameter necessary for the arithmetic process of the data stream held by the control stream transferred to the buffer memory, and

wherein the data transfer control apparatus controls data transfer of the data stream and the control stream between the outside of the data transfer control apparatus and the buffer memory in parallel to the arithmetic process by the processor for the data stream in the buffer memory.

15. The stream processing apparatus according to claim 14, further comprising a control unit which performs control on the basis of an analysis result of the control stream stored in the buffer memory,

wherein the control unit sets transfer conditions to the data transfer control apparatus on the basis of the information on where to obtain the data stream held by the control stream.

16. The stream processing apparatus according to claim 14, further comprising a data memory into/from which data can be written or read by the processor,

wherein the control unit sets a parameter necessary for the arithmetic process of the data stream held by the control stream to the data memory.

17. The stream processing apparatus according to claim 14, further comprising a data memory into/from which data can be written or read by the processor,

wherein the data memory can perform an address conversion process when being accessed from the processor, and the address conversion is a process in which when a process of one data stream is completed and a process of the next data stream is started, logical addresses mapped to a memory area where one data stream is stored and a memory area where the other data stream is stored are switched to each other.

18. The stream processing apparatus according to claim 14, further comprising an instruction memory for storing a program showing the arithmetic procedure of the processor,

wherein the instruction memory can perform an address conversion process when being accessed from the processor, and the address conversion is a process in which when a process of one data stream is completed and a process of the next data stream is started, logical addresses mapped to a memory area where the program showing the arithmetic procedure for one data stream is stored and a memory area where the program showing the arithmetic procedure for the next data stream is stored are switched to each other.

19. A stream processing method in which an arithmetic process is performed for a data stream to output the result as a data stream, the stream processing method comprising the steps of:

preparing, as information necessary for the stream process, information on where to obtain the data stream to be processed and one or more control streams each containing a parameter necessary for a process of the data stream;

referring to the data stream in accordance with the information on where to obtain the data stream of the prepared control stream; and

performing an arithmetic process by referring to the parameter of the prepared control stream.

20. A data processing system comprising:

a stream processing apparatus which inputs a data stream to perform an arithmetic process and outputs the result as a data stream;

a memory in which a control stream and the data stream are stored as information necessary in a stream process for the data stream; and

a host processor which controls the memory and the stream processing apparatus,

wherein the control stream contains information on where to obtain the data stream to be input and a parameter necessary for the arithmetic process of the data stream, and

wherein the stream processing apparatus includes a buffer memory and a processor, inputs the control stream from the memory to the buffer memory, and inputs the data stream to the buffer memory in accordance with the information on where to obtain the data stream held by the input control stream, and the processor performs the arithmetic process for the data stream input to the buffer memory on the basis of the parameter of the control stream.

21. The data processing system according to claim 20,

wherein the host processor performs control to store the control stream and the data stream into the memory, and

wherein the stream processing apparatus includes a transfer control apparatus which transfers the control stream and the data stream from the memory to the buffer memory.

22. The data processing system according to claim 20, being formed over one semiconductor substrate as a semiconductor device.