ERROR CORRECTING CODE PREDICATION SYSTEM AND METHOD

• US 20090144598A1
• Filed: 01/30/2008
• Published: 06/04/2009
• Est. Priority Date: 11/30/2007
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Azimi, Saeed, Yoon, Tony
• Granted Patent: US 8,429,492 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

In memory devices that degrade with use, a memory controller may monitor and record a usage history of portions of the memory. The memory controller can then vary a strength of error correction coding to protect information written to various portions of the memory having different usage histories. More specifically, and memory can receive information to be stored in the memory, select a portion of memory to store the information, and store the information in the selected portion of the memory with an error correction coding having a strength that is based on a usage history of the selected portion of the memory.

Claims

1. A method of storing information comprising:

receiving information to be stored in a memory;

selecting a portion of the memory to store the information; and

storing the information in the selected portion of the memory with an error correction coding having a strength that is based on a usage history of the selected portion of the memory.

2. The method according to claim 1, wherein storing the information in the selected portion of the memory further comprises:

storing the information in the memory as a block that includes both the information and parity bits.

3. The method according to claim 2, wherein a ratio of information bits to information bits plus parity bits decreases as the strength of the error correction coding increases.

4. The method according to claim 3, wherein the size of the block is fixed, so that as the ratio of information bits to information bits plus parity bits decreases, an amount of information stored in the block decreases.

5. The method according to claim 4, further comprising:

storing spillover information in another portion of the memory when the amount of information stored in the block decreases.

6. The method according to claim 5, wherein the spillover information is stored in a reserved portion of the memory.

7. The method according to claim 6, wherein the spillover information is stored in the reserved portion of the memory with an error correction coding having a strength that is based on usage history of the reserved memory portion.

8. The method according to claim 1, wherein selecting a portion of the memory to store the information, further comprises:

examining the usage history of available portions of the memory; and

allocating a portion of the memory having a usage history indicating less use before a portion of the memory having a usage history indicating more use.

9. The method according to claim 1, wherein selecting a portion of the memory to store the information, further comprises:

examining usage history of available portions of the memory; and

allocating a portion of the memory having a usage history indicating less erasures before a portion of the memory having a usage history indicating more erasures.

10. The method according to claim 1, wherein selecting a portion of the memory to store the information, further comprises:

examining usage history of available portions of the memory; and

allocating a portion of the memory having a usage history indicating a higher reliability before a portion of the memory having a usage history indicating a lesser reliability.

11. The method according to claim 1, further comprising:

storing usage history corresponding to respective portions of the memory, wherein the usage history includes one or more states of the portions of the memory.

12. The method according to claim 11, wherein the states of the portions of the memory include a number of times a portion of the memory has been erased.

13. The method according to claim 11, wherein the states of the portions of the memory include at least one of whether a portion of the memory is unusable, unreliable and usable.

14. The method according to claim 6, wherein the spillover information is stored in the reserved portion of the memory with an error correction coding having a same strength as that of the selected portion of the memory.

15. The method according to claim 1, further comprising:

determining whether the usage history exceeds a usage threshold; and

if so, adjusting the strength of the error correction coding based on the determination.

16. The method according to claim 15, wherein the usage threshold is a number of times the selected portion of the memory has been erased.

17. The method according to claim 15, wherein adjusting the strength of the error correction coding includes increasing a number of parity bits that are stored with the information.

18. The method according to claim 15, wherein adjusting the strength of the error correction coding includes using an error correction code that is stronger than the error correction coding currently associated with the selected portion of the memory.

19. The method according to claim 1, further comprising:

determining a range based on the usage history; and

setting the strength of the error correction coding to a level based on the range.

20. The method according to claim 19, wherein a first level of the error correction coding includes less parity bits than a second level of error correction coding.

21. The method according to claim 19, wherein the error correction coding includes at least one of Hamming, BCH, and Reed-Solomon code.

22. The method according to claim 19, wherein a first level of the error correction coding includes one of Hamming, BCH, and Reed-Solomon code and a second level of the error correction coding includes a different one of Hamming, BCH, and Reed-Solomon code,

23. The method according to claim 1, wherein the error correction coding includes at least one of Hamming, BCH, and Reed-Solomon code.

24. The method according to claim 1, wherein selecting a portion of the memory to store the information, further comprises:

selecting a portion of the memory having a lower strength error correction code before a portion of the memory having a greater strength error correction code.

25. A method of storing information comprising:

receiving information;

selecting a portion of a memory to store the information;

designating an error correction coding strength based on a usage history of the selected portion of the memory;

coding the information with an error correction coding having the designated error correction coding strength; and

storing the coded information in the selected portion of the memory.

26. The method according to claim 25, wherein designating the error correction coding strength based on the usage history, further comprises:

determining whether the usage history is within a first range;

if so, setting the strength of the error correction coding to a first level;

determining whether the usage history is within a second range; and

if so, setting the strength of the error correction coding to a second level.

27. The method according to claim 26, wherein the first level of the error correction coding includes less parity bits than the second level of error correction coding.

28. The method according to claim 26, wherein the error correction coding includes at least one of Hamming, BCH, and Reed-Solomon code.

29. The method according to claim 26, wherein the first level of the error correction coding includes one of Hamming, BCH, and Reed-Solomon code and the second level of the error correction coding includes a different one of Hamming, BCH, and Reed-Solomon code.

30. The method according to claim 26, wherein the first range is lower than the second range.

31. A device that stores information comprising:

a memory;

a controller that is coupled to the memory that receives information, selects a portion of the memory to store the information, and stores the information in the selected portion of the memory with an error correction coding having a strength that is based on a usage history of the selected portion of the memory.

32. The device according to claim 31, wherein the controller stores the information in the selected portion of the memory as a block that includes both the information and parity bits.

33. The device according to claim 32, wherein a ratio of information bits to information bits plus parity bits decreases as the strength of the error correction coding increases.

34. The device according to claim 33, wherein the size of the block is fixed, so that as the ratio of information bits to information bits plus parity bits decreases, an amount of information stored in the block decreases.

35. The device according to claim 34, wherein the controller stores any spillover information in another portion of the memory when the amount of information stored in the block decreases.

36. The device according to claim 35, further comprising:

a reserve portion of the memory in which the controller stores the spillover information.

37. The device according to claim 36, wherein the controller stores the spillover information in the reserved portion of the memory with an error correction coding having a strength that is based on usage history of the reserved portion of the memory.

38. The device according to claim 31, wherein the controller selects a portion of the memory to store the information by examining usage history of available portions of the memory, and allocating a portion of the memory having a usage history indicating less use before a portion of the memory having a usage history indicating more use.

39. The device according to claim 31, wherein the controller selects a portion of the memory to store the information, by examining usage history of available portions of the memory, and allocating a portion of the memory having a usage history indicating less erasures before a portion of the memory having a usage history indicating more erasures.

40. The device according to claim 31, wherein the controller selects a portion of the memory to store the information, by examining usage history of available portions of the memory, allocating a portion of the memory having a usage history indicating a higher reliability before a portion of the memory having a usage history indicating a lesser reliability.

41. The device according to claim 31, wherein usage history corresponding to the respective portions of the memory includes one or more states of the portions of the memory.

42. The device according to claim 41, wherein states of the portions of the memory include a number of times a portion of the memory has been erased.

43. The device according to claim 41, wherein states of the portions of the memory include at least one of whether the portion of the memory is unusable, unreliable and usable.

44. The device according to claim 36, wherein the controller stores the spillover information in the reserved portion of the memory with an error correction coding having a same strength as that of the selected portion of the memory.

45. The device according to claim 31, wherein the controller by determines whether the usage history exceeds a usage threshold and adjusts the strength of the error correction coding based on the determination.

46. The device according to claim 45, wherein the usage threshold is a number of times the selected portion of the memory has been erased.

47. The device according to claim 45, wherein the controller adjusts the strength of the error correction coding by increasing a number of parity bits that are stored with the information.

48. The device according to claim 45, wherein the controller adjusts the strength of the error correction coding by using an error correction code that is stronger than the error correction coding currently associated with the selected portion of the memory.

49. The device according to claim 31, wherein the controller determines a range based on the usage history, and sets the strength of the error correction coding to a level based on the range.

50. The device according to claim 49, wherein a first level of the error correction coding includes less parity bits than a second level of error correction coding.

51. The device according to claim 49, wherein the error correction coding includes at least one of Hamming, BCH, and Reed-Solomon code.

52. The device according to claim 49, wherein a first level of the error correction coding includes one of Hamming, BCH, and Reed-Solomon code and a second level of the error correction coding includes a different one of Hamming, BCH, and Reed-Solomon code.

53. The device according to claim 31, wherein the error correction coding includes at least one of Hamming, BCH, and Reed-Solomon code.

54. The device according to claim 31, wherein the controller selects a portion of the memory to store the information by selecting a portion of the memory having a lower strength error correction code before a portion of the memory having a greater strength error correction code.