METHOD AND ARRANGEMENT FOR ENHANCING PROCESS VARIABILITY AND LIFETIME RELIABILITY THROUGH 3D INTEGRATION

• US 20090144669A1
• Filed: 11/29/2007
• Published: 06/04/2009
• Est. Priority Date: 11/29/2007
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rivers, Jude A., Bose, Pradip, Kursun, Eren, Zyuban, Victor
• Application Number:
  US11/947,207
• Publication Number:
  US 20090144669A1
• Time in Patent Office: Days
• US Class Current: 716/100
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an arrangement for implementing the inventive method.

Claims

1. A method for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional integration applied to electronic packaging, said method comprising:

(a) providing a first semiconductor chip essentially consisting of a microprocessor, a plurality of performance and memory resources, including selectively functional units, control macros, elements of data flow, register files and memory arrays;

(b) providing one or more second semiconductor chips in a superimposed arrangement over said first semiconductor chip, said second semiconductor chip including an on-chip controller and redundant resources actuatable upon recognition of a faulty resource or plurality of faulty resources on said first semiconductor chip;

(c) configuring at least one of the redundant resources on said second semiconductor chip as a performance enhancer for at least one of the resources on said first semiconductor chip; and

(d) incorporating redundancies on said second semiconductor chip thereon for critical macros on said first semiconductor chip selectively comprising vectors, fixed or floating point execution blocks, auxiliary pipelines and diverse component units.

2. An arrangement for enhancing semiconductor chip lifetime reliability through a three-dimensional integration applied to electronic packaging, said arrangement comprising:

(a) a first semiconductor chip essentially consisting of a microprocessor, a plurality of performance and memory resources, including selectively functional units, control macros, elements of data flow, register files and memory arrays;

(b) a second semiconductor chip being located in a superimposed arrangement over said first semiconductor chip, said second conductor chip including an on-chip controller and redundant resources actuatable upon recognition of a faulty resource or plurality of faulty resources on said first semiconductor chip;

(c) at least one of the redundant resources on said second semiconductor chip being configured as a performance enhancer for at least one of the resources on said first semiconductor chip; and

(d) redundancies incorporated on said second semiconductor chip for critical macros on said first semiconductor chip selectively comprising vectors, fixed or floating point execution blocks, auxiliary pipelines and diverse component units.