METHOD AND ON-CHIP CONTROL APPARATUS FOR ENHANCING PROCESS RELIABILITY AND PROCESS VARIABILITY THROUGH 3D INTEGRATION

• US 20090144678A1
• Filed: 11/30/2007
• Published: 06/04/2009
• Est. Priority Date: 11/30/2007
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Rivers, Jude A., Bose, Pradip, Kursun, Eren, Zyuban, Victor
• Application Number:
  US11/948,376
• Publication Number:
  US 20090144678A1
• Time in Patent Office: Days
• US Class Current: 716/106
• CPC Class Codes: G06F 11/2023 Failover techniques
• CPC Class Codes: G06F 2201/845 Systems in which the redundancy can be transformed in increased performance

Abstract

A method and on-chip controller for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method.

Claims

1. An on-chip method utilizing a controller for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional integration applied to electronic packaging, said method comprising:

(a) providing a first semiconductor chip essentially consisting of a microprocessor, a plurality of performance and memory resources, including selectively functional units, control macros, elements of data flow, register files and memory arrays;

(b) providing a second semiconductor chip in a superimposed arrangement over said first semiconductor chip, said second semiconductor chip including an on-chip controller and redundant resources actuatable upon recognition of a faulty resource or plurality of faulty resources on said first semiconductor chip;

(c) configuring at least one of the redundant resources on said second semiconductor chip as a performance enhancer for at least one of the resources on said first semiconductor chip;

(d) incorporating redundancies on said second semiconductor chip thereon for critical macros on said first semiconductor chip selectively comprising vectors, fixed or floating point execution blocks, auxiliary pipelines and diverse component units; and

(e) having an on-chip controller activate and rewire any encountered on-chip redundancy including configurable redundancies depending upon current malfunctions and/or faults in the semiconductor chip.

2. An on-chip controller arrangement for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional integration applied to electronic packaging, said arrangement comprising:

(a) a first semiconductor chip essentially consisting of a microprocessor, a plurality of performance and memory resources, including selectively functional units, control macros, elements of data flow, register files and memory arrays;

(b) a second semiconductor chip being located in a superimposed arrangement over said first semiconductor chip, said second conductor chip including an on-chip controller and redundant resources actuatable upon recognition of a faulty resource or plurality of faulty resources on said first semiconductor chip;

(c) at least one of the redundant resources on said second semiconductor chip being configured as a performance enhancer for at least one of the resources on said first semiconductor chip;

(d) redundancies on said second semiconductor chip being incorporated for critical macros on said first semiconductor chip selectively comprising vectors, fixed or floating point execution blocks, auxiliary pipelines and diverse component units; and

(e) said on-chip controller activates and rewires any encountered on-chip redundancy including configurable redundancies depending upon current malfunctions and/or faults in the semiconductor chip.